From 6e99a8cb37916dbd2fcc9d150fee006d383a4c54 Mon Sep 17 00:00:00 2001
From: Chad Rosier <mcrosier@apple.com>
Date: Tue, 27 Nov 2012 22:29:43 +0000
Subject: [PATCH] [arm fast-isel] Appease the machine verifier by using the
proper register classes. The vast majority of the remaining issues are due
to uses of invalid registers, which are defined by getRegForValue(). Those
will be a little more challenging to cleanup. rdar://12719844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168735 91177308-0d34-0410-b5e6-96231b3b80d8
---
lib/Target/ARM/ARMFastISel.cpp | 16 +++++++---------
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp
index e972a93687c..8d88f9416bf 100644
--- a/lib/Target/ARM/ARMFastISel.cpp
+++ b/lib/Target/ARM/ARMFastISel.cpp
@@ -2586,26 +2586,24 @@ unsigned ARMFastISel::ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT,
default: return 0;
case MVT::i16:
if (!Subtarget->hasV6Ops()) return 0;
- if (isZExt) {
+ RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
+ if (isZExt)
Opc = isThumb2 ? ARM::t2UXTH : ARM::UXTH;
- } else {
+ else
Opc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
- RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
- }
break;
case MVT::i8:
if (!Subtarget->hasV6Ops()) return 0;
- if (isZExt) {
+ RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
+ if (isZExt)
Opc = isThumb2 ? ARM::t2UXTB : ARM::UXTB;
- } else {
+ else
Opc = isThumb2 ? ARM::t2SXTB : ARM::SXTB;
- RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
- }
break;
case MVT::i1:
if (isZExt) {
- Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
+ Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
isBoolZext = true;
break;
}