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Fixed spelling.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8588 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman
2003-09-17 21:34:23 +00:00
parent a589d31faa
commit 6eba07a6a3
7 changed files with 17 additions and 17 deletions
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4
lib/CodeGen/InstrSched/InstrScheduling.cpp
View File

@@ -1060,7 +1060,7 @@ NodeCanFillDelaySlot(const SchedulingManager& S,
if (! S.getInstrInfo().hasOperandInterlock(node->getOpCode())) if (! S.getInstrInfo().hasOperandInterlock(node->getOpCode()))
return false; return false;
// Finally, if the instruction preceeds the branch, we make sure the // Finally, if the instruction precedes the branch, we make sure the
// instruction can be reordered relative to the branch. We simply check // instruction can be reordered relative to the branch. We simply check
// if the instr. has only 1 outgoing edge, viz., a CD edge to the branch. // if the instr. has only 1 outgoing edge, viz., a CD edge to the branch.
// //
@@ -1092,7 +1092,7 @@ MarkNodeForDelaySlot(SchedulingManager& S,
bool nodeIsPredecessor) bool nodeIsPredecessor)
{ {
if (nodeIsPredecessor) { if (nodeIsPredecessor) {
// If node is in the same basic block (i.e., preceeds brNode), // If node is in the same basic block (i.e., precedes brNode),
// remove it and all its incident edges from the graph. Make sure we // remove it and all its incident edges from the graph. Make sure we
// add dummy edges for pred/succ nodes that become entry/exit nodes. // add dummy edges for pred/succ nodes that become entry/exit nodes.
graph->eraseIncidentEdges(node, /*addDummyEdges*/ true); graph->eraseIncidentEdges(node, /*addDummyEdges*/ true);

2
lib/CodeGen/InstrSelection/InstrForest.cpp
View File

@@ -4,7 +4,7 @@
// tree if one or more of them might be potentially combined into a single // tree if one or more of them might be potentially combined into a single
// complex instruction in the target machine. // complex instruction in the target machine.
// Since this grouping is completely machine-independent, we do it as // Since this grouping is completely machine-independent, we do it as
// aggressive as possible to exploit any possible taret instructions. // aggressive as possible to exploit any possible target instructions.
// In particular, we group two instructions O and I if: // In particular, we group two instructions O and I if:
// (1) Instruction O computes an operand used by instruction I, // (1) Instruction O computes an operand used by instruction I,
// and (2) O and I are part of the same basic block, // and (2) O and I are part of the same basic block,

6
lib/CodeGen/InstrSelection/InstrSelection.cpp
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@@ -81,7 +81,7 @@ TmpInstruction::TmpInstruction(MachineCodeForInstruction& mcfi,
{ {
mcfi.addTemp(this); mcfi.addTemp(this);
Operands.push_back(Use(s1, this)); // s1 must be nonnull Operands.push_back(Use(s1, this)); // s1 must be non-null
if (s2) { if (s2) {
Operands.push_back(Use(s2, this)); Operands.push_back(Use(s2, this));
} }
@@ -239,7 +239,7 @@ InstructionSelection::InsertPhiElimInstructions(BasicBlock *BB,
MachineFunction &MF = MachineFunction::get(BB->getParent()); MachineFunction &MF = MachineFunction::get(BB->getParent());
// FIXME: if PHI instructions existed in the machine code, this would be // FIXME: if PHI instructions existed in the machine code, this would be
// unnecesary. // unnecessary.
MachineBasicBlock *MBB = 0; MachineBasicBlock *MBB = 0;
for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
if (I->getBasicBlock() == BB) { if (I->getBasicBlock() == BB) {
@@ -342,7 +342,7 @@ InstructionSelection::SelectInstructionsForTree(InstrTreeNode* treeRoot,
} }
} }
// Finally, do any postprocessing on this node after its children // Finally, do any post-processing on this node after its children
// have been translated // have been translated
// //
if (treeRoot->opLabel != VRegListOp) if (treeRoot->opLabel != VRegListOp)

10
lib/CodeGen/MachineInstr.cpp
View File

@@ -127,7 +127,7 @@ MachineInstr::SetRegForImplicitRef(unsigned i, int regNum)
} }
// Subsitute all occurrences of Value* oldVal with newVal in all operands // Substitute all occurrences of Value* oldVal with newVal in all operands
// and all implicit refs. // and all implicit refs.
// If defsOnly == true, substitute defs only. // If defsOnly == true, substitute defs only.
unsigned unsigned
@@ -140,7 +140,7 @@ MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
unsigned numSubst = 0; unsigned numSubst = 0;
// Subsitute operands // Substitute operands
for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O) for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
if (*O == oldVal) if (*O == oldVal)
if (!defsOnly || if (!defsOnly ||
@@ -153,7 +153,7 @@ MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
else else
someArgsWereIgnored = true; someArgsWereIgnored = true;
// Subsitute implicit refs // Substitute implicit refs
for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i) for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
if (getImplicitRef(i) == oldVal) if (getImplicitRef(i) == oldVal)
if (!defsOnly || if (!defsOnly ||
@@ -301,7 +301,7 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
OS << "<def>"; OS << "<def>";
} }
// code for printing implict references // code for printing implicit references
if (getNumImplicitRefs()) { if (getNumImplicitRefs()) {
OS << "\tImplicitRefs: "; OS << "\tImplicitRefs: ";
for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) { for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
@@ -330,7 +330,7 @@ std::ostream &operator<<(std::ostream& os, const MachineInstr& MI)
os << "<d&u>"; os << "<d&u>";
} }
// code for printing implict references // code for printing implicit references
unsigned NumOfImpRefs = MI.getNumImplicitRefs(); unsigned NumOfImpRefs = MI.getNumImplicitRefs();
if (NumOfImpRefs > 0) { if (NumOfImpRefs > 0) {
os << "\tImplicit: "; os << "\tImplicit: ";

4
lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
View File

@@ -1060,7 +1060,7 @@ NodeCanFillDelaySlot(const SchedulingManager& S,
if (! S.getInstrInfo().hasOperandInterlock(node->getOpCode())) if (! S.getInstrInfo().hasOperandInterlock(node->getOpCode()))
return false; return false;
// Finally, if the instruction preceeds the branch, we make sure the // Finally, if the instruction precedes the branch, we make sure the
// instruction can be reordered relative to the branch. We simply check // instruction can be reordered relative to the branch. We simply check
// if the instr. has only 1 outgoing edge, viz., a CD edge to the branch. // if the instr. has only 1 outgoing edge, viz., a CD edge to the branch.
// //
@@ -1092,7 +1092,7 @@ MarkNodeForDelaySlot(SchedulingManager& S,
bool nodeIsPredecessor) bool nodeIsPredecessor)
{ {
if (nodeIsPredecessor) { if (nodeIsPredecessor) {
// If node is in the same basic block (i.e., preceeds brNode), // If node is in the same basic block (i.e., precedes brNode),
// remove it and all its incident edges from the graph. Make sure we // remove it and all its incident edges from the graph. Make sure we
// add dummy edges for pred/succ nodes that become entry/exit nodes. // add dummy edges for pred/succ nodes that become entry/exit nodes.
graph->eraseIncidentEdges(node, /*addDummyEdges*/ true); graph->eraseIncidentEdges(node, /*addDummyEdges*/ true);

2
lib/Target/SparcV9/InstrSelection/InstrForest.cpp
View File

@@ -4,7 +4,7 @@
// tree if one or more of them might be potentially combined into a single // tree if one or more of them might be potentially combined into a single
// complex instruction in the target machine. // complex instruction in the target machine.
// Since this grouping is completely machine-independent, we do it as // Since this grouping is completely machine-independent, we do it as
// aggressive as possible to exploit any possible taret instructions. // aggressive as possible to exploit any possible target instructions.
// In particular, we group two instructions O and I if: // In particular, we group two instructions O and I if:
// (1) Instruction O computes an operand used by instruction I, // (1) Instruction O computes an operand used by instruction I,
// and (2) O and I are part of the same basic block, // and (2) O and I are part of the same basic block,

6
lib/Target/SparcV9/InstrSelection/InstrSelection.cpp
View File

@@ -81,7 +81,7 @@ TmpInstruction::TmpInstruction(MachineCodeForInstruction& mcfi,
{ {
mcfi.addTemp(this); mcfi.addTemp(this);
Operands.push_back(Use(s1, this)); // s1 must be nonnull Operands.push_back(Use(s1, this)); // s1 must be non-null
if (s2) { if (s2) {
Operands.push_back(Use(s2, this)); Operands.push_back(Use(s2, this));
} }
@@ -239,7 +239,7 @@ InstructionSelection::InsertPhiElimInstructions(BasicBlock *BB,
MachineFunction &MF = MachineFunction::get(BB->getParent()); MachineFunction &MF = MachineFunction::get(BB->getParent());
// FIXME: if PHI instructions existed in the machine code, this would be // FIXME: if PHI instructions existed in the machine code, this would be
// unnecesary. // unnecessary.
MachineBasicBlock *MBB = 0; MachineBasicBlock *MBB = 0;
for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
if (I->getBasicBlock() == BB) { if (I->getBasicBlock() == BB) {
@@ -342,7 +342,7 @@ InstructionSelection::SelectInstructionsForTree(InstrTreeNode* treeRoot,
} }
} }
// Finally, do any postprocessing on this node after its children // Finally, do any post-processing on this node after its children
// have been translated // have been translated
// //
if (treeRoot->opLabel != VRegListOp) if (treeRoot->opLabel != VRegListOp)