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create a generic bcond instruction that has a conditional code argument

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29856 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2006-08-24 16:13:15 +00:00
parent 0569eee66b
commit 6f602de3b6
4 changed files with 34 additions and 8 deletions
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14
lib/Target/ARM/ARM.h
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@ -20,6 +20,20 @@
#include <cassert> #include <cassert>
namespace llvm { namespace llvm {
// Enums corresponding to ARM condition codes
namespace ARMCC {
enum CondCodes {
NE
};
}
static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
switch (CC) {
default: assert(0 && "Unknown condition code");
case ARMCC::NE: return "ne";
}
}
class FunctionPass; class FunctionPass;
class TargetMachine; class TargetMachine;

3
lib/Target/ARM/ARMAsmPrinter.cpp
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@ -201,7 +201,8 @@ void ARMAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
} }
void ARMAsmPrinter::printCCOperand(const MachineInstr *MI, int opNum) { void ARMAsmPrinter::printCCOperand(const MachineInstr *MI, int opNum) {
assert(0 && "not implemented"); int CC = (int)MI->getOperand(opNum).getImmedValue();
O << ARMCondCodeToString((ARMCC::CondCodes)CC);
} }
bool ARMAsmPrinter::doInitialization(Module &M) { bool ARMAsmPrinter::doInitialization(Module &M) {

13
lib/Target/ARM/ARMISelDAGToDAG.cpp
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@ -79,6 +79,14 @@ namespace llvm {
} }
} }
/// DAGCCToARMCC - Convert a DAG integer condition code to an ARM CC
static ARMCC::CondCodes DAGCCToARMCC(ISD::CondCode CC) {
switch (CC) {
default: assert(0 && "Unknown condition code!");
case ISD::SETNE: return ARMCC::NE;
}
}
const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
switch (Opcode) { switch (Opcode) {
default: return 0; default: return 0;
@ -322,11 +330,10 @@ static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) {
SDOperand LHS = Op.getOperand(2); SDOperand LHS = Op.getOperand(2);
SDOperand RHS = Op.getOperand(3); SDOperand RHS = Op.getOperand(3);
SDOperand Dest = Op.getOperand(4); SDOperand Dest = Op.getOperand(4);
SDOperand ARMCC = DAG.getConstant(DAGCCToARMCC(CC), MVT::i32);
assert(CC == ISD::SETNE);
SDOperand Cmp = DAG.getNode(ARMISD::CMP, MVT::Flag, LHS, RHS); SDOperand Cmp = DAG.getNode(ARMISD::CMP, MVT::Flag, LHS, RHS);
return DAG.getNode(ARMISD::BR, MVT::Other, Chain, Dest, Cmp); return DAG.getNode(ARMISD::BR, MVT::Other, Chain, Dest, ARMCC, Cmp);
} }
SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {

12
lib/Target/ARM/ARMInstrInfo.td
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@ -39,6 +39,10 @@ class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction {
def brtarget : Operand<OtherVT>; def brtarget : Operand<OtherVT>;
// Operand for printing out a condition code.
let PrintMethod = "printCCOperand" in
def CCOp : Operand<i32>;
def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq, def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq,
[SDNPHasChain, SDNPOutFlag]>; [SDNPHasChain, SDNPOutFlag]>;
@ -52,7 +56,7 @@ def retflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
[SDNPHasChain, SDNPOptInFlag]>; [SDNPHasChain, SDNPOptInFlag]>;
def armselect : SDNode<"ARMISD::SELECT", SDTIntBinOp, [SDNPInFlag, SDNPOutFlag]>; def armselect : SDNode<"ARMISD::SELECT", SDTIntBinOp, [SDNPInFlag, SDNPOutFlag]>;
def SDTarmbr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; def SDTarmbr : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
def armbr : SDNode<"ARMISD::BR", SDTarmbr, [SDNPHasChain, SDNPInFlag]>; def armbr : SDNode<"ARMISD::BR", SDTarmbr, [SDNPHasChain, SDNPInFlag]>;
def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
@ -112,9 +116,9 @@ let isTwoAddress = 1 in {
[(set IntRegs:$dst, (armselect IntRegs:$true, IntRegs:$false))]>; [(set IntRegs:$dst, (armselect IntRegs:$true, IntRegs:$false))]>;
} }
def bne : InstARM<(ops brtarget:$dst), def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc),
"bne $dst", "b$cc $dst",
[(armbr bb:$dst)]>; [(armbr bb:$dst, imm:$cc)]>;
def cmp : InstARM<(ops IntRegs:$a, IntRegs:$b), def cmp : InstARM<(ops IntRegs:$a, IntRegs:$b),
"cmp $a, $b", "cmp $a, $b",