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Add various coarse bit-width architecture predicates to llvm::Triple.
These are very useful for frontends and other utilities reasoning about or selecting between triples. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149353 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -241,6 +241,25 @@ public:
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/// @name Convenience Predicates
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/// @{
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/// \brief Test whether the architecture is 64-bit
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///
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/// Note that this tests for 64-bit pointer width, and nothing else. Note
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/// that we intentionally expose only three predicates, 64-bit, 32-bit, and
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/// 16-bit. The inner details of pointer width for particular architectures
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/// is not summed up in the triple, and so only a coarse grained predicate
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/// system is provided.
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bool isArch64Bit() const;
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/// \brief Test whether the architecture is 32-bit
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///
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/// Note that this tests for 32-bit pointer width, and nothing else.
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bool isArch32Bit() const;
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/// \brief Test whether the architecture is 16-bit
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///
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/// Note that this tests for 16-bit pointer width, and nothing else.
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bool isArch16Bit() const;
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/// isOSVersionLT - Helper function for doing comparisons against version
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/// numbers included in the target triple.
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bool isOSVersionLT(unsigned Major, unsigned Minor = 0,
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@ -665,3 +665,52 @@ void Triple::setEnvironmentName(StringRef Str) {
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void Triple::setOSAndEnvironmentName(StringRef Str) {
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setTriple(getArchName() + "-" + getVendorName() + "-" + Str);
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}
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static unsigned getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
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switch (Arch) {
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case llvm::Triple::UnknownArch:
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case llvm::Triple::InvalidArch:
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return 0;
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case llvm::Triple::msp430:
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return 16;
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case llvm::Triple::amdil:
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case llvm::Triple::arm:
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case llvm::Triple::cellspu:
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case llvm::Triple::hexagon:
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case llvm::Triple::le32:
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case llvm::Triple::mblaze:
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case llvm::Triple::mips:
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case llvm::Triple::mipsel:
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case llvm::Triple::ppc:
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case llvm::Triple::ptx32:
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case llvm::Triple::sparc:
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case llvm::Triple::tce:
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case llvm::Triple::thumb:
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case llvm::Triple::x86:
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case llvm::Triple::xcore:
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return 32;
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case llvm::Triple::mips64:
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case llvm::Triple::mips64el:
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case llvm::Triple::ppc64:
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case llvm::Triple::ptx64:
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case llvm::Triple::sparcv9:
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case llvm::Triple::x86_64:
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return 64;
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}
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llvm_unreachable("Invalid architecture value");
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}
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bool Triple::isArch64Bit() const {
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return getArchPointerBitWidth(getArch()) == 64;
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}
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bool Triple::isArch32Bit() const {
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return getArchPointerBitWidth(getArch()) == 32;
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}
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bool Triple::isArch16Bit() const {
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return getArchPointerBitWidth(getArch()) == 16;
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}
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@ -267,4 +267,61 @@ TEST(TripleTest, MutateName) {
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}
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TEST(TripleTest, BitWidthPredicates) {
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Triple T;
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EXPECT_FALSE(T.isArch16Bit());
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EXPECT_FALSE(T.isArch32Bit());
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EXPECT_FALSE(T.isArch64Bit());
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T.setArch(Triple::InvalidArch);
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EXPECT_FALSE(T.isArch16Bit());
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EXPECT_FALSE(T.isArch32Bit());
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EXPECT_FALSE(T.isArch64Bit());
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T.setArch(Triple::arm);
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EXPECT_FALSE(T.isArch16Bit());
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EXPECT_TRUE(T.isArch32Bit());
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EXPECT_FALSE(T.isArch64Bit());
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T.setArch(Triple::hexagon);
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EXPECT_FALSE(T.isArch16Bit());
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EXPECT_TRUE(T.isArch32Bit());
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EXPECT_FALSE(T.isArch64Bit());
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T.setArch(Triple::mips);
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EXPECT_FALSE(T.isArch16Bit());
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EXPECT_TRUE(T.isArch32Bit());
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EXPECT_FALSE(T.isArch64Bit());
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T.setArch(Triple::mips64);
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EXPECT_FALSE(T.isArch16Bit());
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EXPECT_FALSE(T.isArch32Bit());
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EXPECT_TRUE(T.isArch64Bit());
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T.setArch(Triple::msp430);
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EXPECT_TRUE(T.isArch16Bit());
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EXPECT_FALSE(T.isArch32Bit());
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EXPECT_FALSE(T.isArch64Bit());
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T.setArch(Triple::ppc);
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EXPECT_FALSE(T.isArch16Bit());
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EXPECT_TRUE(T.isArch32Bit());
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EXPECT_FALSE(T.isArch64Bit());
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T.setArch(Triple::ppc64);
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EXPECT_FALSE(T.isArch16Bit());
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EXPECT_FALSE(T.isArch32Bit());
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EXPECT_TRUE(T.isArch64Bit());
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T.setArch(Triple::x86);
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EXPECT_FALSE(T.isArch16Bit());
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EXPECT_TRUE(T.isArch32Bit());
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EXPECT_FALSE(T.isArch64Bit());
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T.setArch(Triple::x86_64);
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EXPECT_FALSE(T.isArch16Bit());
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EXPECT_FALSE(T.isArch32Bit());
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EXPECT_TRUE(T.isArch64Bit());
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}
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}
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