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Pseudoinstructions should not be less constrained than the instruction they are

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lowered to. This fixes a lot of verifier failures on the test suite.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142254 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Cameron Zwarich 2011-10-17 21:20:13 +00:00
parent b006337bb8
commit 6f9c28060f
1 changed files with 6 additions and 6 deletions
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12
lib/Target/ARM/ARMInstrThumb2.td
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@ -614,19 +614,19 @@ multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
PatFrag opnode, bit Commutable = 0> {
// shifted imm
def ri : T2sTwoRegImm<
(outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
(outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
opc, ".w\t$Rd, $Rn, $imm",
[(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_imm:$imm))]>;
[(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]>;
// register
def rr : T2sThreeReg<
(outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
opc, ".w\t$Rd, $Rn, $Rm",
[(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, rGPR:$Rm))]>;
[(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn, rGPR:$Rm))]>;
// shifted register
def rs : T2sTwoRegShiftedReg<
(outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
(outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
opc, ".w\t$Rd, $Rn, $ShiftedRm",
[(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]>;
[(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]>;
}
}