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It seems better to scalarize vectors of size 1 instead of widening them.

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Add support to widen SETCC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94342 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Mon P Wang
2010-01-24 00:24:43 +00:00
parent abb992d6a3
commit 6fb474bd3c
4 changed files with 33 additions and 1 deletions
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1
lib/CodeGen/SelectionDAG/LegalizeTypes.h
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@@ -609,6 +609,7 @@ private:
SDValue WidenVecRes_SIGN_EXTEND_INREG(SDNode* N);
SDValue WidenVecRes_SELECT(SDNode* N);
SDValue WidenVecRes_SELECT_CC(SDNode* N);
SDValue WidenVecRes_SETCC(SDNode* N);
SDValue WidenVecRes_UNDEF(SDNode *N);
SDValue WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N);
SDValue WidenVecRes_VSETCC(SDNode* N);

9
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
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@@ -1172,6 +1172,7 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
case ISD::VECTOR_SHUFFLE:
Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
@@ -1718,6 +1719,14 @@ SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
N->getOperand(1), InOp1, InOp2, N->getOperand(4));
}
SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
SDValue InOp1 = GetWidenedVector(N->getOperand(0));
SDValue InOp2 = GetWidenedVector(N->getOperand(1));
return DAG.getNode(ISD::SETCC, N->getDebugLoc(), WidenVT,
InOp1, InOp2, N->getOperand(2));
}
SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
return DAG.getUNDEF(WidenVT);

2
lib/CodeGen/SelectionDAG/TargetLowering.cpp
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@@ -682,7 +682,7 @@ void TargetLowering::computeRegisterProperties() {
for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
EVT SVT = (MVT::SimpleValueType)nVT;
if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT &&
SVT.getVectorNumElements() > NElts) {
SVT.getVectorNumElements() > NElts && NElts != 1) {
TransformToType[i] = SVT;
ValueTypeActions.setTypeAction(VT, Promote);
IsLegalWiderType = true;

22
test/CodeGen/X86/vsplit-and.ll Normal file
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@@ -0,0 +1,22 @@
; RUN: llc < %s -march=x86 -disable-mmx | FileCheck %s
define void @t(<2 x i64>* %dst, <2 x i64> %src1, <2 x i64> %src2) nounwind readonly {
; CHECK: andb
%cmp1 = icmp ne <2 x i64> %src1, zeroinitializer
%cmp2 = icmp ne <2 x i64> %src2, zeroinitializer
%t1 = and <2 x i1> %cmp1, %cmp2
%t2 = sext <2 x i1> %t1 to <2 x i64>
store <2 x i64> %t2, <2 x i64>* %dst
ret void
}
define void @t2(<3 x i64>* %dst, <3 x i64> %src1, <3 x i64> %src2) nounwind readonly {
; CHECK: andb
%cmp1 = icmp ne <3 x i64> %src1, zeroinitializer
%cmp2 = icmp ne <3 x i64> %src2, zeroinitializer
%t1 = and <3 x i1> %cmp1, %cmp2
%t2 = sext <3 x i1> %t1 to <3 x i64>
store <3 x i64> %t2, <3 x i64>* %dst
ret void
}