From 6fe6905df2e23e284faa9b368fbce096476d7e09 Mon Sep 17 00:00:00 2001 From: Misha Brukman Date: Sat, 7 Jun 2003 02:34:43 +0000 Subject: [PATCH] Do not hastily change the Opcode from 'r' to 'i' type if we're not actually SETTING the operand to be an immediate or have verified that one of the operands is really a SignExtended or Unextended immediate value already, which warrants an 'i' opcode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6662 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../InstrSelection/InstrSelectionSupport.cpp | 13 ++++++------- .../InstrSelection/InstrSelectionSupport.cpp | 13 ++++++------- 2 files changed, 12 insertions(+), 14 deletions(-) diff --git a/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp b/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp index 86a7e7042cd..8f35be8a07d 100644 --- a/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp +++ b/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp @@ -186,12 +186,6 @@ FixConstantOperandsForInstr(Instruction* vmInstr, immedValue); if (opType == MachineOperand::MO_VirtualRegister) constantThatMustBeLoaded = true; - else { - // The optype has changed from being a register to an immediate - // This means we need to change the opcode, e.g. ADDr -> ADDi - unsigned newOpcode = convertOpcodeFromRegToImm(opCode); - minstr->setOpcode(newOpcode); - } } } else @@ -209,7 +203,8 @@ FixConstantOperandsForInstr(Instruction* vmInstr, opCode, target, (immedPos == (int)op), machineRegNum, immedValue); - if (opType == MachineOperand::MO_SignExtendedImmed) { + if (opType == MachineOperand::MO_SignExtendedImmed || + opType == MachineOperand::MO_UnextendedImmed) { // The optype is an immediate value // This means we need to change the opcode, e.g. ADDr -> ADDi unsigned newOpcode = convertOpcodeFromRegToImm(opCode); @@ -233,6 +228,10 @@ FixConstantOperandsForInstr(Instruction* vmInstr, else if (opType == MachineOperand::MO_SignExtendedImmed || opType == MachineOperand::MO_UnextendedImmed) { minstr->SetMachineOperandConst(op, opType, immedValue); + // The optype is or has become an immediate + // This means we need to change the opcode, e.g. ADDr -> ADDi + unsigned newOpcode = convertOpcodeFromRegToImm(opCode); + minstr->setOpcode(newOpcode); } else if (constantThatMustBeLoaded || (opValue && isa(opValue))) { // opValue is a constant that must be explicitly loaded into a reg diff --git a/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp b/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp index 86a7e7042cd..8f35be8a07d 100644 --- a/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp +++ b/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp @@ -186,12 +186,6 @@ FixConstantOperandsForInstr(Instruction* vmInstr, immedValue); if (opType == MachineOperand::MO_VirtualRegister) constantThatMustBeLoaded = true; - else { - // The optype has changed from being a register to an immediate - // This means we need to change the opcode, e.g. ADDr -> ADDi - unsigned newOpcode = convertOpcodeFromRegToImm(opCode); - minstr->setOpcode(newOpcode); - } } } else @@ -209,7 +203,8 @@ FixConstantOperandsForInstr(Instruction* vmInstr, opCode, target, (immedPos == (int)op), machineRegNum, immedValue); - if (opType == MachineOperand::MO_SignExtendedImmed) { + if (opType == MachineOperand::MO_SignExtendedImmed || + opType == MachineOperand::MO_UnextendedImmed) { // The optype is an immediate value // This means we need to change the opcode, e.g. ADDr -> ADDi unsigned newOpcode = convertOpcodeFromRegToImm(opCode); @@ -233,6 +228,10 @@ FixConstantOperandsForInstr(Instruction* vmInstr, else if (opType == MachineOperand::MO_SignExtendedImmed || opType == MachineOperand::MO_UnextendedImmed) { minstr->SetMachineOperandConst(op, opType, immedValue); + // The optype is or has become an immediate + // This means we need to change the opcode, e.g. ADDr -> ADDi + unsigned newOpcode = convertOpcodeFromRegToImm(opCode); + minstr->setOpcode(newOpcode); } else if (constantThatMustBeLoaded || (opValue && isa(opValue))) { // opValue is a constant that must be explicitly loaded into a reg