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ARM cleanup of remaining extend instructions.

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Refactor the rest of the extend instructions to not artificially distinguish
between a rotate of zero and a rotate of any other value. Replace the by-zero
versions with Pat<>'s for ISel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136226 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2011-07-27 17:48:13 +00:00
parent c5a8c861c9
commit 7032741e7b
2 changed files with 121 additions and 170 deletions
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95
lib/Target/ARM/ARMInstrInfo.td
View File

@@ -1011,56 +1011,30 @@ class AI_ext_rrot_np<bits<8> opcod, string opc>
/// AI_exta_rrot - A binary operation with two forms: one whose operand is a /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
/// register and one whose operand is a register rotated by 8/16/24. /// register and one whose operand is a register rotated by 8/16/24.
multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> { class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, rot_imm:$rot),
IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm", IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
[(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>, [(set GPR:$Rd, (opnode GPR:$Rn, (rotr GPR:$Rm, rot_imm:$rot)))]>,
Requires<[IsARM, HasV6]> { Requires<[IsARM, HasV6]> {
bits<4> Rd; bits<4> Rd;
bits<4> Rm; bits<4> Rm;
bits<4> Rn; bits<4> Rn;
let Inst{19-16} = Rn; bits<2> rot;
let Inst{15-12} = Rd; let Inst{19-16} = Rn;
let Inst{11-10} = 0b00; let Inst{15-12} = Rd;
let Inst{9-4} = 0b000111; let Inst{11-10} = rot;
let Inst{3-0} = Rm; let Inst{9-4} = 0b000111;
} let Inst{3-0} = Rm;
def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
rot_imm:$rot),
IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
[(set GPR:$Rd, (opnode GPR:$Rn,
(rotr GPR:$Rm, rot_imm:$rot)))]>,
Requires<[IsARM, HasV6]> {
bits<4> Rd;
bits<4> Rm;
bits<4> Rn;
bits<2> rot;
let Inst{19-16} = Rn;
let Inst{15-12} = Rd;
let Inst{11-10} = rot;
let Inst{9-4} = 0b000111;
let Inst{3-0} = Rm;
}
} }
// For disassembly only. class AI_exta_rrot_np<bits<8> opcod, string opc>
multiclass AI_exta_rrot_np<bits<8> opcod, string opc> { : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, rot_imm:$rot),
def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm", Requires<[IsARM, HasV6]> {
[/* For disassembly only; pattern left blank */]>, bits<4> Rn;
Requires<[IsARM, HasV6]> { bits<2> rot;
let Inst{11-10} = 0b00; let Inst{19-16} = Rn;
} let Inst{11-10} = rot;
def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
rot_imm:$rot),
IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
[/* For disassembly only; pattern left blank */]>,
Requires<[IsARM, HasV6]> {
bits<4> Rn;
bits<2> rot;
let Inst{19-16} = Rn;
let Inst{11-10} = rot;
}
} }
/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube. /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
@@ -2377,14 +2351,14 @@ def SXTB : AI_ext_rrot<0b01101010,
def SXTH : AI_ext_rrot<0b01101011, def SXTH : AI_ext_rrot<0b01101011,
"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
defm SXTAB : AI_exta_rrot<0b01101010, def SXTAB : AI_exta_rrot<0b01101010,
"sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
defm SXTAH : AI_exta_rrot<0b01101011, def SXTAH : AI_exta_rrot<0b01101011,
"sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">; def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">; def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
// Zero extenders // Zero extenders
@@ -2405,15 +2379,14 @@ def UXTB16 : AI_ext_rrot<0b01101100,
def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
(UXTB16 GPR:$Src, 1)>; (UXTB16 GPR:$Src, 1)>;
defm UXTAB : AI_exta_rrot<0b01101110, "uxtab", def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
defm UXTAH : AI_exta_rrot<0b01101111, "uxtah", def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
} }
// This isn't safe in general, the add is two 16-bit units, not a 32-bit add. // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
// For disassembly only def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
def SBFX : I<(outs GPR:$Rd), def SBFX : I<(outs GPR:$Rd),
@@ -4265,14 +4238,24 @@ def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
Requires<[IsARM, HasV6]>; Requires<[IsARM, HasV6]>;
// SXT/UXT with no rotate // SXT/UXT with no rotate
let AddedComplexity = 16 in {
def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>; def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>; def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
let AddedComplexity = 10 in
def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>; def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
(UXTAB GPR:$Rn, GPR:$Rm, 0)>;
def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
(UXTAH GPR:$Rn, GPR:$Rm, 0)>;
}
def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>; def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>; def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPR:$Rm, i8)),
(SXTAB GPR:$Rn, GPR:$Rm, 0)>;
def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPR:$Rm, i16)),
(SXTAH GPR:$Rn, GPR:$Rm, 0)>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Thumb Support // Thumb Support
// //

196
lib/Target/ARM/ARMInstrThumb2.td
View File

@@ -993,116 +993,64 @@ class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
} }
// UXTB16 - Requres T2ExtractPack, does not need the .w qualifier. // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
multiclass T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> { class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr, : T2TwoReg<(outs rGPR:$dst), (ins rGPR:$Rm, rot_imm:$rot),
opc, "\t$Rd, $Rm", IIC_iEXTr, opc, "\t$dst, $Rm$rot",
[(set rGPR:$Rd, (opnode rGPR:$Rm))]>, [(set rGPR:$dst, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
Requires<[HasT2ExtractPack, IsThumb2]> { Requires<[HasT2ExtractPack, IsThumb2]> {
let Inst{31-27} = 0b11111; bits<2> rot;
let Inst{26-23} = 0b0100; let Inst{31-27} = 0b11111;
let Inst{22-20} = opcod; let Inst{26-23} = 0b0100;
let Inst{19-16} = 0b1111; // Rn let Inst{22-20} = opcod;
let Inst{15-12} = 0b1111; let Inst{19-16} = 0b1111; // Rn
let Inst{7} = 1; let Inst{15-12} = 0b1111;
let Inst{5-4} = 0b00; // rotate let Inst{7} = 1;
} let Inst{5-4} = rot;
def r_rot : T2TwoReg<(outs rGPR:$dst), (ins rGPR:$Rm, rot_imm:$rot),
IIC_iEXTr, opc, "\t$dst, $Rm$rot",
[(set rGPR:$dst, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
Requires<[HasT2ExtractPack, IsThumb2]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100;
let Inst{22-20} = opcod;
let Inst{19-16} = 0b1111; // Rn
let Inst{15-12} = 0b1111;
let Inst{7} = 1;
bits<2> rot;
let Inst{5-4} = rot{1-0}; // rotate
}
} }
// SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
// supported yet. // supported yet.
multiclass T2I_ext_rrot_sxtb16<bits<3> opcod, string opc> { class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
def r : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr, : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
opc, "\t$Rd, $Rm", []>, opc, "\t$Rd, $Rm$rot", []>,
Requires<[IsThumb2, HasT2ExtractPack]> { Requires<[IsThumb2, HasT2ExtractPack]> {
let Inst{31-27} = 0b11111; bits<2> rot;
let Inst{26-23} = 0b0100; let Inst{31-27} = 0b11111;
let Inst{22-20} = opcod; let Inst{26-23} = 0b0100;
let Inst{19-16} = 0b1111; // Rn let Inst{22-20} = opcod;
let Inst{15-12} = 0b1111; let Inst{19-16} = 0b1111; // Rn
let Inst{7} = 1; let Inst{15-12} = 0b1111;
let Inst{5-4} = 0b00; // rotate let Inst{7} = 1;
} let Inst{5-4} = rot;
def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$rot), IIC_iEXTr,
opc, "\t$Rd, $Rm, ror $rot", []>,
Requires<[IsThumb2, HasT2ExtractPack]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100;
let Inst{22-20} = opcod;
let Inst{19-16} = 0b1111; // Rn
let Inst{15-12} = 0b1111;
let Inst{7} = 1;
bits<2> rot;
let Inst{5-4} = rot{1-0}; // rotate
}
} }
/// T2I_exta_rrot - A binary operation with two forms: one whose operand is a /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
/// register and one whose operand is a register rotated by 8/16/24. /// register and one whose operand is a register rotated by 8/16/24.
multiclass T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode> { class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr, : T2ThreeReg<(outs rGPR:$Rd),
opc, "\t$Rd, $Rn, $Rm", (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
[(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>, IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
Requires<[HasT2ExtractPack, IsThumb2]> { [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
let Inst{31-27} = 0b11111; Requires<[HasT2ExtractPack, IsThumb2]> {
let Inst{26-23} = 0b0100; bits<2> rot;
let Inst{22-20} = opcod; let Inst{31-27} = 0b11111;
let Inst{15-12} = 0b1111; let Inst{26-23} = 0b0100;
let Inst{7} = 1; let Inst{22-20} = opcod;
let Inst{5-4} = 0b00; // rotate let Inst{15-12} = 0b1111;
} let Inst{7} = 1;
def rr_rot : T2ThreeReg<(outs rGPR:$Rd), let Inst{5-4} = rot;
(ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
[(set rGPR:$Rd, (opnode rGPR:$Rn,
(rotr rGPR:$Rm, rot_imm:$rot)))]>,
Requires<[HasT2ExtractPack, IsThumb2]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100;
let Inst{22-20} = opcod;
let Inst{15-12} = 0b1111;
let Inst{7} = 1;
bits<2> rot;
let Inst{5-4} = rot{1-0}; // rotate
}
} }
multiclass T2I_exta_rrot_np<bits<3> opcod, string opc> { class T2I_exta_rrot_np<bits<3> opcod, string opc>
def rr : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr, : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
opc, "\t$Rd, $Rn, $Rm", []> { IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
let Inst{31-27} = 0b11111; bits<2> rot;
let Inst{26-23} = 0b0100; let Inst{31-27} = 0b11111;
let Inst{22-20} = opcod; let Inst{26-23} = 0b0100;
let Inst{15-12} = 0b1111; let Inst{22-20} = opcod;
let Inst{7} = 1; let Inst{15-12} = 0b1111;
let Inst{5-4} = 0b00; // rotate let Inst{7} = 1;
} let Inst{5-4} = rot;
def rr_rot :T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100;
let Inst{22-20} = opcod;
let Inst{15-12} = 0b1111;
let Inst{7} = 1;
bits<2> rot;
let Inst{5-4} = rot{1-0}; // rotate
}
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@@ -1661,15 +1609,15 @@ def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
UnOpFrag<(sext_inreg node:$Src, i8)>>; UnOpFrag<(sext_inreg node:$Src, i8)>>;
def t2SXTH : T2I_ext_rrot<0b000, "sxth", def t2SXTH : T2I_ext_rrot<0b000, "sxth",
UnOpFrag<(sext_inreg node:$Src, i16)>>; UnOpFrag<(sext_inreg node:$Src, i16)>>;
defm t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">; def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
defm t2SXTAB : T2I_exta_rrot<0b100, "sxtab", def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
defm t2SXTAH : T2I_exta_rrot<0b000, "sxtah", def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
defm t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">; def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
// TODO: SXT(A){B|H}16 - done for disassembly only // TODO: SXT(A){B|H}16
// Zero extenders // Zero extenders
@@ -1678,7 +1626,7 @@ def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
UnOpFrag<(and node:$Src, 0x000000FF)>>; UnOpFrag<(and node:$Src, 0x000000FF)>>;
def t2UXTH : T2I_ext_rrot<0b001, "uxth", def t2UXTH : T2I_ext_rrot<0b001, "uxth",
UnOpFrag<(and node:$Src, 0x0000FFFF)>>; UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
defm t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16", def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
UnOpFrag<(and node:$Src, 0x00FF00FF)>>; UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
// FIXME: This pattern incorrectly assumes the shl operator is a rotate. // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
@@ -1686,17 +1634,17 @@ defm t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
// instead so we can include a check for masking back in the upper // instead so we can include a check for masking back in the upper
// eight bits of the source into the lower eight bits of the result. // eight bits of the source into the lower eight bits of the result.
//def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF), //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
// (t2UXTB16r_rot rGPR:$Src, 3)>, // (t2UXTB16 rGPR:$Src, 3)>,
// Requires<[HasT2ExtractPack, IsThumb2]>; // Requires<[HasT2ExtractPack, IsThumb2]>;
def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF), def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
(t2UXTB16r_rot rGPR:$Src, 1)>, (t2UXTB16 rGPR:$Src, 1)>,
Requires<[HasT2ExtractPack, IsThumb2]>; Requires<[HasT2ExtractPack, IsThumb2]>;
defm t2UXTAB : T2I_exta_rrot<0b101, "uxtab", def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
defm t2UXTAH : T2I_exta_rrot<0b001, "uxtah", def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
defm t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">; def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@@ -3458,8 +3406,28 @@ def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
// //
// SXT/UXT with no rotate // SXT/UXT with no rotate
def : T2Pat<(and rGPR:$Src, 0x000000FF), (t2UXTB rGPR:$Src, 0)>; let AddedComplexity = 16 in {
def : T2Pat<(and rGPR:$Src, 0x0000FFFF), (t2UXTH rGPR:$Src, 0)>; def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
Requires<[HasT2ExtractPack, IsThumb2]>;
def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
Requires<[HasT2ExtractPack, IsThumb2]>;
def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
Requires<[HasT2ExtractPack, IsThumb2]>;
def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
(t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
Requires<[HasT2ExtractPack, IsThumb2]>;
def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
(t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
Requires<[HasT2ExtractPack, IsThumb2]>;
}
def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>; def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>; Requires<[HasT2ExtractPack, IsThumb2]>;
def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
Requires<[HasT2ExtractPack, IsThumb2]>;
def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
(t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
Requires<[HasT2ExtractPack, IsThumb2]>;
def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
(t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
Requires<[HasT2ExtractPack, IsThumb2]>;