mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-04-03 02:31:26 +00:00
Start converting NEON load/stores to use pseudo instructions, beginning here
with the VST4 instructions. Until after register allocation, we want to represent sets of adjacent registers by a single super-register. These VST4 pseudo instructions have a single QQ or QQQQ source register operand. They get expanded to the real VST4 instructions with 4 separate D register operands. Once this conversion is complete, we'll be able to remove the NEONPreAllocPass and avoid some fragile and hacky code elsewhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112108 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
parent
5b5f7260a0
commit
709d59255a
@ -24,6 +24,13 @@ using namespace llvm;
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namespace {
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class ARMExpandPseudo : public MachineFunctionPass {
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// Constants for register spacing in NEON load/store instructions.
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enum NEONRegSpacing {
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SingleSpc,
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EvenDblSpc,
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OddDblSpc
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};
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public:
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static char ID;
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ARMExpandPseudo() : MachineFunctionPass(ID) {}
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@ -41,6 +48,8 @@ namespace {
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void TransferImpOps(MachineInstr &OldMI,
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MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
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bool ExpandMBB(MachineBasicBlock &MBB);
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void ExpandVST4(MachineBasicBlock::iterator &MBBI, unsigned Opc,
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bool hasWriteBack, NEONRegSpacing RegSpc);
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};
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char ARMExpandPseudo::ID = 0;
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}
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@ -63,6 +72,61 @@ void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
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}
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}
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/// ExpandVST4 - Translate VST4 pseudo instructions with QQ or QQQQ register
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/// operands to real VST4 instructions with 4 D register operands.
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void ARMExpandPseudo::ExpandVST4(MachineBasicBlock::iterator &MBBI,
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unsigned Opc, bool hasWriteBack,
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NEONRegSpacing RegSpc) {
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MachineInstr &MI = *MBBI;
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MachineBasicBlock &MBB = *MI.getParent();
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MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
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unsigned OpIdx = 0;
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if (hasWriteBack) {
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bool DstIsDead = MI.getOperand(OpIdx).isDead();
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unsigned DstReg = MI.getOperand(OpIdx++).getReg();
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MIB.addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead));
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}
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// Copy the addrmode6 operands.
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bool AddrIsKill = MI.getOperand(OpIdx).isKill();
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MIB.addReg(MI.getOperand(OpIdx++).getReg(), getKillRegState(AddrIsKill));
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MIB.addImm(MI.getOperand(OpIdx++).getImm());
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if (hasWriteBack) {
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// Copy the am6offset operand.
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bool OffsetIsKill = MI.getOperand(OpIdx).isKill();
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MIB.addReg(MI.getOperand(OpIdx++).getReg(), getKillRegState(OffsetIsKill));
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}
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bool SrcIsKill = MI.getOperand(OpIdx).isKill();
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unsigned SrcReg = MI.getOperand(OpIdx).getReg();
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unsigned D0, D1, D2, D3;
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if (RegSpc == SingleSpc) {
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D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
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D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
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D2 = TRI->getSubReg(SrcReg, ARM::dsub_2);
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D3 = TRI->getSubReg(SrcReg, ARM::dsub_3);
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} else if (RegSpc == EvenDblSpc) {
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D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
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D1 = TRI->getSubReg(SrcReg, ARM::dsub_2);
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D2 = TRI->getSubReg(SrcReg, ARM::dsub_4);
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D3 = TRI->getSubReg(SrcReg, ARM::dsub_6);
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} else {
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assert(RegSpc == OddDblSpc && "unknown register spacing for VST4");
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D0 = TRI->getSubReg(SrcReg, ARM::dsub_1);
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D1 = TRI->getSubReg(SrcReg, ARM::dsub_3);
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D2 = TRI->getSubReg(SrcReg, ARM::dsub_5);
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D3 = TRI->getSubReg(SrcReg, ARM::dsub_7);
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}
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MIB.addReg(D0, getKillRegState(SrcIsKill))
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.addReg(D1, getKillRegState(SrcIsKill))
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.addReg(D2, getKillRegState(SrcIsKill))
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.addReg(D3, getKillRegState(SrcIsKill));
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MIB = AddDefaultPred(MIB);
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TransferImpOps(MI, MIB, MIB);
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MI.eraseFromParent();
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}
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bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
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bool Modified = false;
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@ -71,9 +135,13 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
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MachineInstr &MI = *MBBI;
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MachineBasicBlock::iterator NMBBI = llvm::next(MBBI);
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bool ModifiedOp = true;
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unsigned Opcode = MI.getOpcode();
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switch (Opcode) {
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default: break;
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default:
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ModifiedOp = false;
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break;
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case ARM::tLDRpci_pic:
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case ARM::t2LDRpci_pic: {
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unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
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@ -92,7 +160,6 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
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.addOperand(MI.getOperand(2));
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TransferImpOps(MI, MIB1, MIB2);
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MI.eraseFromParent();
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Modified = true;
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break;
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}
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@ -128,7 +195,6 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
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HI16.addImm(Pred).addReg(PredReg);
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TransferImpOps(MI, LO16, HI16);
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MI.eraseFromParent();
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Modified = true;
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break;
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}
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@ -155,9 +221,37 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
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.addReg(OddSrc, getKillRegState(SrcIsKill)));
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TransferImpOps(MI, Even, Odd);
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MI.eraseFromParent();
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}
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case ARM::VST4d8Pseudo:
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ExpandVST4(MBBI, ARM::VST4d8, false, SingleSpc); break;
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case ARM::VST4d16Pseudo:
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ExpandVST4(MBBI, ARM::VST4d16, false, SingleSpc); break;
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case ARM::VST4d32Pseudo:
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ExpandVST4(MBBI, ARM::VST4d32, false, SingleSpc); break;
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case ARM::VST4d8Pseudo_UPD:
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ExpandVST4(MBBI, ARM::VST4d8_UPD, true, SingleSpc); break;
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case ARM::VST4d16Pseudo_UPD:
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ExpandVST4(MBBI, ARM::VST4d16_UPD, true, SingleSpc); break;
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case ARM::VST4d32Pseudo_UPD:
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ExpandVST4(MBBI, ARM::VST4d32_UPD, true, SingleSpc); break;
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case ARM::VST4q8Pseudo_UPD:
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ExpandVST4(MBBI, ARM::VST4q8_UPD, true, EvenDblSpc); break;
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case ARM::VST4q16Pseudo_UPD:
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ExpandVST4(MBBI, ARM::VST4q16_UPD, true, EvenDblSpc); break;
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case ARM::VST4q32Pseudo_UPD:
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ExpandVST4(MBBI, ARM::VST4q32_UPD, true, EvenDblSpc); break;
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case ARM::VST4q8oddPseudo_UPD:
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ExpandVST4(MBBI, ARM::VST4q8_UPD, true, OddDblSpc); break;
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case ARM::VST4q16oddPseudo_UPD:
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ExpandVST4(MBBI, ARM::VST4q16_UPD, true, OddDblSpc); break;
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case ARM::VST4q32oddPseudo_UPD:
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ExpandVST4(MBBI, ARM::VST4q32_UPD, true, OddDblSpc); break;
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break;
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}
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if (ModifiedOp)
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Modified = true;
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}
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}
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MBBI = NMBBI;
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}
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@ -1260,6 +1260,11 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
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Ops.push_back(MemAddr);
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Ops.push_back(Align);
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// FIXME: This is a temporary flag to distinguish VSTs that have been
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// converted to pseudo instructions.
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bool usePseudoInstrs = (NumVecs == 4 &&
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VT.getSimpleVT().SimpleTy != MVT::v1i64);
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if (is64BitVector) {
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if (NumVecs >= 2) {
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SDValue RegSeq;
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@ -1278,6 +1283,9 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
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: N->getOperand(3+3);
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RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
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}
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if (usePseudoInstrs)
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Ops.push_back(RegSeq);
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else {
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// Now extract the D registers back out.
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, VT,
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@ -1290,15 +1298,16 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
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if (NumVecs > 3)
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, VT,
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RegSeq));
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}
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} else {
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for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
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Ops.push_back(N->getOperand(Vec+3));
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Ops.push_back(N->getOperand(3));
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}
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Ops.push_back(Pred);
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Ops.push_back(Reg0); // predicate register
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Ops.push_back(Chain);
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unsigned Opc = DOpcodes[OpcodeIndex];
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return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+5);
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return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(),
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usePseudoInstrs ? 6 : NumVecs+5);
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}
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EVT RegVT = GetNEONSubregVT(VT);
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@ -1363,6 +1372,9 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
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// Store the even D registers.
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assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
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Ops.push_back(Reg0); // post-access address offset
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if (usePseudoInstrs)
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Ops.push_back(RegSeq);
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else
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for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0+Vec*2, dl,
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RegVT, RegSeq));
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@ -1371,18 +1383,24 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
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Ops.push_back(Chain);
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unsigned Opc = QOpcodes0[OpcodeIndex];
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SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
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MVT::Other, Ops.data(), NumVecs+6);
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MVT::Other, Ops.data(),
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usePseudoInstrs ? 7 : NumVecs+6);
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Chain = SDValue(VStA, 1);
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// Store the odd D registers.
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Ops[0] = SDValue(VStA, 0); // MemAddr
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if (usePseudoInstrs)
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Ops[6] = Chain;
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else {
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for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
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Ops[Vec+3] = CurDAG->getTargetExtractSubreg(ARM::dsub_1+Vec*2, dl,
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RegVT, RegSeq);
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Ops[NumVecs+5] = Chain;
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}
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Opc = QOpcodes1[OpcodeIndex];
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SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
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MVT::Other, Ops.data(), NumVecs+6);
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MVT::Other, Ops.data(),
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usePseudoInstrs ? 7 : NumVecs+6);
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Chain = SDValue(VStB, 1);
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ReplaceUses(SDValue(N, 0), Chain);
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return NULL;
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@ -2312,14 +2330,14 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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}
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case Intrinsic::arm_neon_vst4: {
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unsigned DOpcodes[] = { ARM::VST4d8, ARM::VST4d16,
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ARM::VST4d32, ARM::VST1d64Q };
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unsigned QOpcodes0[] = { ARM::VST4q8_UPD,
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ARM::VST4q16_UPD,
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ARM::VST4q32_UPD };
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unsigned QOpcodes1[] = { ARM::VST4q8odd_UPD,
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ARM::VST4q16odd_UPD,
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ARM::VST4q32odd_UPD };
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unsigned DOpcodes[] = { ARM::VST4d8Pseudo, ARM::VST4d16Pseudo,
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ARM::VST4d32Pseudo, ARM::VST1d64Q };
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unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
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ARM::VST4q16Pseudo_UPD,
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ARM::VST4q32Pseudo_UPD };
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unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
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ARM::VST4q16oddPseudo_UPD,
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ARM::VST4q32oddPseudo_UPD };
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return SelectVST(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
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}
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@ -1534,6 +1534,14 @@ class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
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let Inst{7-4} = op7_4;
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}
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class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
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: InstARM<AddrMode6, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr,
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itin> {
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let OutOperandList = oops;
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let InOperandList = !con(iops, (ins pred:$p));
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list<Predicate> Predicates = [HasNEON];
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}
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class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string dt, string asm, string cstr, list<dag> pattern>
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: NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
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@ -486,6 +486,19 @@ def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32">;
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let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
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// Classes for VST* pseudo-instructions with multi-register operands.
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// These are expanded to real instructions after register allocation.
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class VSTQQPseudo
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: PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), IIC_VST, "">;
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class VSTQQWBPseudo
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: PseudoNLdSt<(outs GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset, QQPR:$src), IIC_VST,
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"$addr.addr = $wb">;
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class VSTQQQQWBPseudo
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: PseudoNLdSt<(outs GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), IIC_VST,
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"$addr.addr = $wb">;
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// VST1 : Vector Store (multiple single elements)
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class VST1D<bits<4> op7_4, string Dt>
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: NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$addr, DPR:$src), IIC_VST,
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@ -664,6 +677,10 @@ def VST4d8 : VST4D<0b0000, 0b0000, "8">;
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def VST4d16 : VST4D<0b0000, 0b0100, "16">;
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def VST4d32 : VST4D<0b0000, 0b1000, "32">;
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def VST4d8Pseudo : VSTQQPseudo;
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def VST4d16Pseudo : VSTQQPseudo;
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def VST4d32Pseudo : VSTQQPseudo;
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// ...with address register writeback:
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class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
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: NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
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@ -676,6 +693,10 @@ def VST4d8_UPD : VST4DWB<0b0000, 0b0000, "8">;
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def VST4d16_UPD : VST4DWB<0b0000, 0b0100, "16">;
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def VST4d32_UPD : VST4DWB<0b0000, 0b1000, "32">;
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def VST4d8Pseudo_UPD : VSTQQWBPseudo;
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def VST4d16Pseudo_UPD : VSTQQWBPseudo;
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def VST4d32Pseudo_UPD : VSTQQWBPseudo;
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// ...with double-spaced registers (non-updating versions for disassembly only):
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def VST4q8 : VST4D<0b0001, 0b0000, "8">;
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def VST4q16 : VST4D<0b0001, 0b0100, "16">;
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@ -684,10 +705,14 @@ def VST4q8_UPD : VST4DWB<0b0001, 0b0000, "8">;
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def VST4q16_UPD : VST4DWB<0b0001, 0b0100, "16">;
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def VST4q32_UPD : VST4DWB<0b0001, 0b1000, "32">;
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def VST4q8Pseudo_UPD : VSTQQQQWBPseudo;
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def VST4q16Pseudo_UPD : VSTQQQQWBPseudo;
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def VST4q32Pseudo_UPD : VSTQQQQWBPseudo;
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// ...alternate versions to be allocated odd register numbers:
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def VST4q8odd_UPD : VST4DWB<0b0001, 0b0000, "8">;
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def VST4q16odd_UPD : VST4DWB<0b0001, 0b0100, "16">;
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def VST4q32odd_UPD : VST4DWB<0b0001, 0b1000, "32">;
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def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo;
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def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo;
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def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo;
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// VST1LN : Vector Store (single element from one lane)
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// FIXME: Not yet implemented.
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@ -260,9 +260,6 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
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Stride = 2;
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return true;
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case ARM::VST4d8:
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case ARM::VST4d16:
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case ARM::VST4d32:
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case ARM::VST1d64Q:
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case ARM::VST4LNd8:
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case ARM::VST4LNd16:
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@ -271,24 +268,6 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
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NumRegs = 4;
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return true;
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case ARM::VST4q8_UPD:
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case ARM::VST4q16_UPD:
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case ARM::VST4q32_UPD:
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FirstOpnd = 4;
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NumRegs = 4;
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Offset = 0;
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Stride = 2;
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return true;
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case ARM::VST4q8odd_UPD:
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case ARM::VST4q16odd_UPD:
|
||||
case ARM::VST4q32odd_UPD:
|
||||
FirstOpnd = 4;
|
||||
NumRegs = 4;
|
||||
Offset = 1;
|
||||
Stride = 2;
|
||||
return true;
|
||||
|
||||
case ARM::VST4LNq16:
|
||||
case ARM::VST4LNq32:
|
||||
FirstOpnd = 2;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user