6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-06 06:33:24 +00:00
Code Issues Projects Releases Wiki Activity

Use pseudo instructions for VST1d64Q.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112170 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2010-08-26 05:33:30 +00:00
parent 8de3bdb16a
commit 70e48b23a3
4 changed files with 9 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/ARM/ARMExpandPseudoInsts.cpp
View File

@ -229,12 +229,16 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
ExpandVST4(MBBI, ARM::VST4d16, false, SingleSpc); break;
case ARM::VST4d32Pseudo:
ExpandVST4(MBBI, ARM::VST4d32, false, SingleSpc); break;
case ARM::VST1d64QPseudo:
ExpandVST4(MBBI, ARM::VST1d64Q, false, SingleSpc); break;
case ARM::VST4d8Pseudo_UPD:
ExpandVST4(MBBI, ARM::VST4d8_UPD, true, SingleSpc); break;
case ARM::VST4d16Pseudo_UPD:
ExpandVST4(MBBI, ARM::VST4d16_UPD, true, SingleSpc); break;
case ARM::VST4d32Pseudo_UPD:
ExpandVST4(MBBI, ARM::VST4d32_UPD, true, SingleSpc); break;
case ARM::VST1d64QPseudo_UPD:
ExpandVST4(MBBI, ARM::VST1d64Q_UPD, true, SingleSpc); break;
case ARM::VST4q8Pseudo_UPD:
ExpandVST4(MBBI, ARM::VST4q8_UPD, true, EvenDblSpc); break;
case ARM::VST4q16Pseudo_UPD:

5
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -1262,8 +1262,7 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
// FIXME: This is a temporary flag to distinguish VSTs that have been
// converted to pseudo instructions.
bool usePseudoInstrs = (NumVecs == 4 &&
VT.getSimpleVT().SimpleTy != MVT::v1i64);
bool usePseudoInstrs = (NumVecs == 4);
if (is64BitVector) {
if (NumVecs >= 2) {
@ -2331,7 +2330,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
case Intrinsic::arm_neon_vst4: {
unsigned DOpcodes[] = { ARM::VST4d8Pseudo, ARM::VST4d16Pseudo,
ARM::VST4d32Pseudo, ARM::VST1d64Q };
ARM::VST4d32Pseudo, ARM::VST1d64QPseudo };
unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
ARM::VST4q16Pseudo_UPD,
ARM::VST4q32Pseudo_UPD };

3
lib/Target/ARM/ARMInstrNEON.td
View File

@ -583,6 +583,9 @@ def VST1d16Q_UPD : VST1D4WB<0b0100, "16">;
def VST1d32Q_UPD : VST1D4WB<0b1000, "32">;
def VST1d64Q_UPD : VST1D4WB<0b1100, "64">;
def VST1d64QPseudo : VSTQQPseudo;
def VST1d64QPseudo_UPD : VSTQQWBPseudo;
// VST2 : Vector Store (multiple 2-element structures)
class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
: NLdSt<0, 0b00, op11_8, op7_4, (outs),

1
lib/Target/ARM/NEONPreAllocPass.cpp
View File

@ -260,7 +260,6 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
Stride = 2;
return true;
case ARM::VST1d64Q:
case ARM::VST4LNd8:
case ARM::VST4LNd16:
case ARM::VST4LNd32: