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[Hexagon] Replacing some load patterns with cleaner versions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228169 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
2015-02-04 19:05:32 +00:00
parent 8f260e3084
commit 70e83e3a1c
1 changed files with 13 additions and 59 deletions
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72
lib/Target/Hexagon/HexagonInstrInfoV4.td
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@@ -548,54 +548,20 @@ defm loadrd : ld_idxd_shl<"memd", "LDrid", DoubleRegs, 0b110>;
// 'def pats' for load instructions with base + register offset and non-zero // 'def pats' for load instructions with base + register offset and non-zero
// immediate value. Immediate value is used to left-shift the second // immediate value. Immediate value is used to left-shift the second
// register operand. // register operand.
class Loadxs_pat<PatFrag Load, ValueType VT, InstHexagon MI>
: Pat<(VT (Load (add (i32 IntRegs:$Rs),
(i32 (shl (i32 IntRegs:$Rt), u2ImmPred:$u2))))),
(VT (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2))>;
let AddedComplexity = 40 in { let AddedComplexity = 40 in {
def : Pat <(i32 (sextloadi8 (add IntRegs:$src1, def: Loadxs_pat<extloadi8, i32, L4_loadrub_rr>;
(shl IntRegs:$src2, u2ImmPred:$offset)))), def: Loadxs_pat<zextloadi8, i32, L4_loadrub_rr>;
(L4_loadrb_rr IntRegs:$src1, def: Loadxs_pat<sextloadi8, i32, L4_loadrb_rr>;
IntRegs:$src2, u2ImmPred:$offset)>, def: Loadxs_pat<extloadi16, i32, L4_loadruh_rr>;
Requires<[HasV4T]>; def: Loadxs_pat<zextloadi16, i32, L4_loadruh_rr>;
def: Loadxs_pat<sextloadi16, i32, L4_loadrh_rr>;
def : Pat <(i32 (zextloadi8 (add IntRegs:$src1, def: Loadxs_pat<load, i32, L4_loadri_rr>;
(shl IntRegs:$src2, u2ImmPred:$offset)))), def: Loadxs_pat<load, i64, L4_loadrd_rr>;
(L4_loadrub_rr IntRegs:$src1,
IntRegs:$src2, u2ImmPred:$offset)>,
Requires<[HasV4T]>;
def : Pat <(i32 (extloadi8 (add IntRegs:$src1,
(shl IntRegs:$src2, u2ImmPred:$offset)))),
(L4_loadrub_rr IntRegs:$src1,
IntRegs:$src2, u2ImmPred:$offset)>,
Requires<[HasV4T]>;
def : Pat <(i32 (sextloadi16 (add IntRegs:$src1,
(shl IntRegs:$src2, u2ImmPred:$offset)))),
(L4_loadrh_rr IntRegs:$src1,
IntRegs:$src2, u2ImmPred:$offset)>,
Requires<[HasV4T]>;
def : Pat <(i32 (zextloadi16 (add IntRegs:$src1,
(shl IntRegs:$src2, u2ImmPred:$offset)))),
(L4_loadruh_rr IntRegs:$src1,
IntRegs:$src2, u2ImmPred:$offset)>,
Requires<[HasV4T]>;
def : Pat <(i32 (extloadi16 (add IntRegs:$src1,
(shl IntRegs:$src2, u2ImmPred:$offset)))),
(L4_loadruh_rr IntRegs:$src1,
IntRegs:$src2, u2ImmPred:$offset)>,
Requires<[HasV4T]>;
def : Pat <(i32 (load (add IntRegs:$src1,
(shl IntRegs:$src2, u2ImmPred:$offset)))),
(L4_loadri_rr IntRegs:$src1,
IntRegs:$src2, u2ImmPred:$offset)>,
Requires<[HasV4T]>;
def : Pat <(i64 (load (add IntRegs:$src1,
(shl IntRegs:$src2, u2ImmPred:$offset)))),
(L4_loadrd_rr IntRegs:$src1,
IntRegs:$src2, u2ImmPred:$offset)>,
Requires<[HasV4T]>;
} }
// 'def pats' for load instruction base + register offset and // 'def pats' for load instruction base + register offset and
@@ -4033,18 +3999,6 @@ def : Pat<(store (i32 IntRegs:$src1), u0AlwaysExtPred:$src2),
let Predicates = [HasV4T], AddedComplexity = 30 in { let Predicates = [HasV4T], AddedComplexity = 30 in {
def : Pat<(i32 (load u0AlwaysExtPred:$src)), def : Pat<(i32 (load u0AlwaysExtPred:$src)),
(L4_loadri_abs u0AlwaysExtPred:$src)>; (L4_loadri_abs u0AlwaysExtPred:$src)>;
def : Pat<(i32 (sextloadi8 u0AlwaysExtPred:$src)),
(L4_loadrb_abs u0AlwaysExtPred:$src)>;
def : Pat<(i32 (zextloadi8 u0AlwaysExtPred:$src)),
(L4_loadrub_abs u0AlwaysExtPred:$src)>;
def : Pat<(i32 (sextloadi16 u0AlwaysExtPred:$src)),
(L4_loadrh_abs u0AlwaysExtPred:$src)>;
def : Pat<(i32 (zextloadi16 u0AlwaysExtPred:$src)),
(L4_loadruh_abs u0AlwaysExtPred:$src)>;
} }
// Indexed store word - global address. // Indexed store word - global address.