From 71e353ed3530a5da48c3dd3257c410f6c4ce2e3e Mon Sep 17 00:00:00 2001 From: Alkis Evlogimenos Date: Thu, 26 Feb 2004 22:00:20 +0000 Subject: [PATCH] Uncomment assertions that register# != 0 on calls to MRegisterInfo::is{Physical,Virtual}Register. Apply appropriate fixes to relevant files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11882 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/MRegisterInfo.h | 4 ++-- lib/CodeGen/LiveIntervalAnalysis.cpp | 4 ++-- lib/CodeGen/LiveVariables.cpp | 6 +++--- lib/CodeGen/RegAllocLocal.cpp | 30 +++++++++++++++++----------- lib/Target/X86/InstSelectSimple.cpp | 9 +++++---- lib/Target/X86/X86ISelSimple.cpp | 9 +++++---- 6 files changed, 35 insertions(+), 27 deletions(-) diff --git a/include/llvm/Target/MRegisterInfo.h b/include/llvm/Target/MRegisterInfo.h index 0f2f9ad453c..bfac1a8325d 100644 --- a/include/llvm/Target/MRegisterInfo.h +++ b/include/llvm/Target/MRegisterInfo.h @@ -141,14 +141,14 @@ public: /// isPhysicalRegister - Return true if the specified register number is in /// the physical register namespace. static bool isPhysicalRegister(unsigned Reg) { -// assert(Reg && "this is not a register!"); + assert(Reg && "this is not a register!"); return Reg < FirstVirtualRegister; } /// isVirtualRegister - Return true if the specified register number is in /// the virtual register namespace. static bool isVirtualRegister(unsigned Reg) { -// assert(Reg && "this is not a register!"); + assert(Reg && "this is not a register!"); return Reg >= FirstVirtualRegister; } diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp index 024ff12ea54..fc46de2be92 100644 --- a/lib/CodeGen/LiveIntervalAnalysis.cpp +++ b/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -134,7 +134,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { mii != mie; ) { for (unsigned i = 0; i < mii->getNumOperands(); ++i) { const MachineOperand& mop = mii->getOperand(i); - if (mop.isRegister()) { + if (mop.isRegister() && mop.getReg()) { // replace register with representative register unsigned reg = rep(mop.getReg()); mii->SetMachineOperandReg(i, reg); @@ -421,7 +421,7 @@ void LiveIntervals::computeIntervals() for (int i = mi->getNumOperands() - 1; i >= 0; --i) { MachineOperand& mop = mi->getOperand(i); // handle register defs - build intervals - if (mop.isRegister() && mop.isDef()) + if (mop.isRegister() && mop.getReg() && mop.isDef()) handleRegisterDef(mbb, mi, mop.getReg()); } } diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp index 361b5038a2b..35c64e25484 100644 --- a/lib/CodeGen/LiveVariables.cpp +++ b/lib/CodeGen/LiveVariables.cpp @@ -232,7 +232,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) { // Process all explicit uses... for (unsigned i = 0; i != NumOperandsToProcess; ++i) { MachineOperand &MO = MI->getOperand(i); - if (MO.isUse() && MO.isRegister()) { + if (MO.isUse() && MO.isRegister() && MO.getReg()) { if (MRegisterInfo::isVirtualRegister(MO.getReg())){ HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI); } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) && @@ -250,7 +250,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) { // Process all explicit defs... for (unsigned i = 0; i != NumOperandsToProcess; ++i) { MachineOperand &MO = MI->getOperand(i); - if (MO.isDef() && MO.isRegister()) { + if (MO.isDef() && MO.isRegister() && MO.getReg()) { if (MRegisterInfo::isVirtualRegister(MO.getReg())) { VarInfo &VRInfo = getVarInfo(MO.getReg()); @@ -325,7 +325,7 @@ void LiveVariables::instructionChanged(MachineInstr *OldMI, // the instruction. for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) { MachineOperand &MO = NewMI->getOperand(i); - if (MO.isRegister() && MO.isDef() && + if (MO.isRegister() && MO.isDef() && MO.getReg() && MRegisterInfo::isVirtualRegister(MO.getReg())) { unsigned Reg = MO.getReg(); VarInfo &VI = getVarInfo(Reg); diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp index 37d600ef81d..bd1e090a6fe 100644 --- a/lib/CodeGen/RegAllocLocal.cpp +++ b/lib/CodeGen/RegAllocLocal.cpp @@ -542,11 +542,13 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) { // physical register is referenced by the instruction, that it is guaranteed // to be live-in, or the input is badly hosed. // - for (unsigned i = 0; i != MI->getNumOperands(); ++i) - if (MI->getOperand(i).isUse() && - !MI->getOperand(i).isDef() && MI->getOperand(i).isRegister() && - MRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg())) + for (unsigned i = 0; i != MI->getNumOperands(); ++i) { + MachineOperand& MO = MI->getOperand(i); + // here we are looking for only used operands (never def&use) + if (!MO.isDef() && MO.isRegister() && MO.getReg() && + MRegisterInfo::isVirtualRegister(MO.getReg())) MI = reloadVirtReg(MBB, MI, i); + } // If this instruction is the last user of anything in registers, kill the // value, freeing the register being used, so it doesn't need to be @@ -573,10 +575,11 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) { // Loop over all of the operands of the instruction, spilling registers that // are defined, and marking explicit destinations in the PhysRegsUsed map. - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) - if (MI->getOperand(i).isDef() && MI->getOperand(i).isRegister() && - MRegisterInfo::isPhysicalRegister(MI->getOperand(i).getReg())) { - unsigned Reg = MI->getOperand(i).getReg(); + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand& MO = MI->getOperand(i); + if (MO.isDef() && MO.isRegister() && MO.getReg() && + MRegisterInfo::isPhysicalRegister(MO.getReg())) { + unsigned Reg = MO.getReg(); spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in the reg PhysRegsUsed[Reg] = 0; // It is free and reserved now PhysRegsUseOrder.push_back(Reg); @@ -586,6 +589,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) { PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now } } + } // Loop over the implicit defs, spilling them as well. for (const unsigned *ImplicitDefs = TID.ImplicitDefs; @@ -606,10 +610,11 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) { // implicit defs and assign them to a register, spilling incoming values if // we need to scavenge a register. // - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) - if (MI->getOperand(i).isDef() && MI->getOperand(i).isRegister() && - MRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg())) { - unsigned DestVirtReg = MI->getOperand(i).getReg(); + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand& MO = MI->getOperand(i); + if (MO.isDef() && MO.isRegister() && MO.getReg() && + MRegisterInfo::isVirtualRegister(MO.getReg())) { + unsigned DestVirtReg = MO.getReg(); unsigned DestPhysReg; // If DestVirtReg already has a value, use it. @@ -618,6 +623,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) { markVirtRegModified(DestVirtReg); MI->SetMachineOperandReg(i, DestPhysReg); // Assign the output register } + } // If this instruction defines any registers that are immediately dead, // kill them now. diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp index 34ffb67bef1..2c247c223a2 100644 --- a/lib/Target/X86/InstSelectSimple.cpp +++ b/lib/Target/X86/InstSelectSimple.cpp @@ -696,14 +696,15 @@ void ISel::InsertFPRegKills() { for (MachineFunction::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) { for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I!=E; ++I) - for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) - if (I->getOperand(i).isRegister()) { - unsigned Reg = I->getOperand(i).getReg(); + for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { + MachineOperand& MO = I->getOperand(i); + if (MO.isRegister() && MO.getReg()) { + unsigned Reg = MO.getReg(); if (MRegisterInfo::isVirtualRegister(Reg)) if (RegMap.getRegClass(Reg)->getSize() == 10) goto UsesFPReg; } - + } // If we haven't found an FP register use or def in this basic block, check // to see if any of our successors has an FP PHI node, which will cause a // copy to be inserted into this block. diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp index 34ffb67bef1..2c247c223a2 100644 --- a/lib/Target/X86/X86ISelSimple.cpp +++ b/lib/Target/X86/X86ISelSimple.cpp @@ -696,14 +696,15 @@ void ISel::InsertFPRegKills() { for (MachineFunction::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) { for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I!=E; ++I) - for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) - if (I->getOperand(i).isRegister()) { - unsigned Reg = I->getOperand(i).getReg(); + for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { + MachineOperand& MO = I->getOperand(i); + if (MO.isRegister() && MO.getReg()) { + unsigned Reg = MO.getReg(); if (MRegisterInfo::isVirtualRegister(Reg)) if (RegMap.getRegClass(Reg)->getSize() == 10) goto UsesFPReg; } - + } // If we haven't found an FP register use or def in this basic block, check // to see if any of our successors has an FP PHI node, which will cause a // copy to be inserted into this block.