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Reapply r146997, "Heed spill slot alignment on ARM."

Browse Source 
Now that canRealignStack() understands frozen reserved registers, it is
safe to use it for aligned spill instructions.

It will only return true if the registers reserved at the beginning of
register allocation allow for dynamic stack realignment.

<rdar://problem/10625436>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147579 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2012-01-05 00:26:57 +00:00
parent 54f3b7a910
commit 7255a4e133
4 changed files with 6 additions and 6 deletions
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5
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -765,7 +765,8 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
break;
case 16:
if (ARM::QPRRegClass.hasSubClassEq(RC)) {
if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
// Use aligned spills if the stack can be realigned.
if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo))
.addFrameIndex(FI).addImm(16)
.addReg(SrcReg, getKillRegState(isKill))
@ -914,7 +915,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
break;
case 16:
if (ARM::QPRRegClass.hasSubClassEq(RC)) {
if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg)
.addFrameIndex(FI).addImm(16)
.addMemOperand(MMO));

2
lib/Target/ARM/ARMBaseRegisterInfo.cpp
View File

@ -557,7 +557,7 @@ needsStackRealignment(const MachineFunction &MF) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
const Function *F = MF.getFunction();
unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) ||
bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
F->hasFnAttr(Attribute::StackAlignment));
return requiresRealignment && canRealignStack(MF);

3
test/CodeGen/ARM/fast-isel-deadcode.ll
View File

@ -15,8 +15,7 @@ entry:
; THUMB-NOT: sxtb
; THUMB: movs r0, #0
; THUMB: movt r0, #0
; THUMB: add sp, #32
; THUMb: pop {r7, pc}
; THUMB: pop
ret i32 0
}

2
test/CodeGen/Thumb2/aligned-spill.ll
View File

@ -1,4 +1,4 @@
; DONT: llc < %s -mcpu=cortex-a8 | FileCheck %s
; RUN: llc < %s -mcpu=cortex-a8 | FileCheck %s
; RUN: llc < %s -mcpu=cortex-a8 -align-neon-spills | FileCheck %s --check-prefix=NEON
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
target triple = "thumbv7-apple-ios"