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Inline isShuffleMaskLegal into LowerVECTOR_SHUFFLE, so we can start

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checking each standalone condition and decide whether emit target
specific nodes or remove the condition if it's already matched before.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113031 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2010-09-03 23:24:06 +00:00
parent 597dad35b8
commit 7256e22f77
1 changed files with 23 additions and 4 deletions
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27
lib/Target/X86/X86ISelLowering.cpp
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@ -5475,10 +5475,29 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp)) if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
return CommuteVectorShuffle(SVOp, DAG); return CommuteVectorShuffle(SVOp, DAG);
// Check for legal shuffle and return? // The checks below are all present in isShuffleMaskLegal, but they are
SmallVector<int, 16> PermMask; // inlined here right now to enable us to directly emit target specific
SVOp->getMask(PermMask); // nodes, and remove one by one until they don't return Op anymore.
if (isShuffleMaskLegal(PermMask, VT)) SmallVector<int, 16> M;
SVOp->getMask(M);
// Very little shuffling can be done for 64-bit vectors right now.
if (VT.getSizeInBits() == 64)
return isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ? Op : SDValue();
// FIXME: pshufb, blends, shifts.
if (VT.getVectorNumElements() == 2 ||
ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
isMOVLMask(M, VT) ||
isSHUFPMask(M, VT) ||
isPSHUFDMask(M, VT) ||
isPSHUFHWMask(M, VT) ||
isPSHUFLWMask(M, VT) ||
isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
isUNPCKLMask(M, VT) ||
isUNPCKHMask(M, VT) ||
isUNPCKL_v_undef_Mask(M, VT) ||
isUNPCKH_v_undef_Mask(M, VT))
return Op; return Op;
// Handle v8i16 specifically since SSE can do byte extraction and insertion. // Handle v8i16 specifically since SSE can do byte extraction and insertion.