6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-04-13 15:37:24 +00:00
Code Issues Projects Releases Wiki Activity

When splitting a VAARG, remember its alignment.

Browse Source 
This produces terrible but correct code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106952 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2010-06-26 18:22:20 +00:00
parent de4fe23139
commit 72d13ff755
6 changed files with 51 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
include/llvm/CodeGen/ISDOpcodes.h
View File

@ -508,8 +508,9 @@ namespace ISD {
CALLSEQ_START, // Beginning of a call sequence
CALLSEQ_END, // End of a call sequence
// VAARG - VAARG has three operands: an input chain, a pointer, and a
// SRCVALUE. It returns a pair of values: the vaarg value and a new chain.
// VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE,
// and the alignment. It returns a pair of values: the vaarg value and a
// new chain.
VAARG,
// VACOPY - VACOPY has five operands: an input chain, a destination pointer,

2
include/llvm/CodeGen/SelectionDAG.h
View File

@ -582,7 +582,7 @@ public:
/// getVAArg - VAArg produces a result and token chain, and takes a pointer
/// and a source value as input.
SDValue getVAArg(EVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr,
SDValue SV);
SDValue SV, unsigned Align = 0);
/// getAtomic - Gets a node for an atomic op, produces result and chain and
/// takes 3 operands

20
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -2642,15 +2642,29 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
EVT VT = Node->getValueType(0);
Tmp1 = Node->getOperand(0);
Tmp2 = Node->getOperand(1);
SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0,
false, false, 0);
unsigned Align = Node->getConstantOperandVal(3);
SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0,
false, false, 0);
SDValue VAList = VAListLoad;
if (Align != 0 ) {
VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
DAG.getConstant(Align - 1,
TLI.getPointerTy()));
VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList,
DAG.getConstant(-Align,
TLI.getPointerTy()));
}
// Increment the pointer, VAList, to the next vaarg
Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
DAG.getConstant(TLI.getTargetData()->
getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
TLI.getPointerTy()));
// Store the incremented VAList to the legalized pointer
Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0,
Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2, V, 0,
false, false, 0);
// Load the actual argument out of the pointer VAList
Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0,

9
lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
View File

@ -238,12 +238,17 @@ void DAGTypeLegalizer::ExpandRes_NormalLoad(SDNode *N, SDValue &Lo,
}
void DAGTypeLegalizer::ExpandRes_VAARG(SDNode *N, SDValue &Lo, SDValue &Hi) {
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
EVT OVT = N->getValueType(0);
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), OVT);
SDValue Chain = N->getOperand(0);
SDValue Ptr = N->getOperand(1);
DebugLoc dl = N->getDebugLoc();
const unsigned OldAlign = N->getConstantOperandVal(3);
const Type *Type = OVT.getTypeForEVT(*DAG.getContext());
const unsigned TypeAlign = TLI.getTargetData()->getABITypeAlignment(Type);
const unsigned Align = std::max(OldAlign, TypeAlign);
Lo = DAG.getVAArg(NVT, dl, Chain, Ptr, N->getOperand(2));
Lo = DAG.getVAArg(NVT, dl, Chain, Ptr, N->getOperand(2), Align);
Hi = DAG.getVAArg(NVT, dl, Lo.getValue(1), Ptr, N->getOperand(2));
// Handle endianness of the load.

7
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -4141,9 +4141,10 @@ SelectionDAG::getIndexedStore(SDValue OrigStore, DebugLoc dl, SDValue Base,
SDValue SelectionDAG::getVAArg(EVT VT, DebugLoc dl,
SDValue Chain, SDValue Ptr,
SDValue SV) {
SDValue Ops[] = { Chain, Ptr, SV };
return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 3);
SDValue SV,
unsigned Align) {
SDValue Ops[] = { Chain, Ptr, SV, getTargetConstant(Align, MVT::i32) };
return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 4);
}
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,

19
test/CodeGen/ARM/va_arg.ll Normal file
View File

@ -0,0 +1,19 @@
; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi | FileCheck %s
; Test that we correctly align elements when using va_arg
; CHECK: add r0, r0, #7
; CHECK: bfc r0, #0, #3
define i64 @f8(i32 %i, ...) nounwind optsize {
entry:
%g = alloca i8*, align 4
%g1 = bitcast i8** %g to i8*
call void @llvm.va_start(i8* %g1)
%0 = va_arg i8** %g, i64
call void @llvm.va_end(i8* %g1)
ret i64 %0
}
declare void @llvm.va_start(i8*) nounwind
declare void @llvm.va_end(i8*) nounwind