6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-26 21:32:10 +00:00
Code Issues Projects Releases Wiki Activity

[ARM64] Correctly select ANDWri in FastISel.

Browse Source 
http://reviews.llvm.org/D3598


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207917 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Joey Gouly 2014-05-03 17:27:06 +00:00
parent 81f28f603a
commit 72e96a51bf
2 changed files with 14 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
lib/Target/ARM64/ARM64FastISel.cpp
View File

@ -577,7 +577,8 @@ bool ARM64FastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
// Loading an i1 requires special handling.
if (VTIsi1) {
unsigned ANDReg = createResultReg(&ARM64::GPR32RegClass);
MRI.constrainRegClass(ResultReg, &ARM64::GPR32RegClass);
unsigned ANDReg = createResultReg(&ARM64::GPR32spRegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM64::ANDWri),
ANDReg)
.addReg(ResultReg)
@ -665,7 +666,8 @@ bool ARM64FastISel::EmitStore(MVT VT, unsigned SrcReg, Address Addr,
// Storing an i1 requires special handling.
if (VTIsi1) {
unsigned ANDReg = createResultReg(&ARM64::GPR32RegClass);
MRI.constrainRegClass(SrcReg, &ARM64::GPR32RegClass);
unsigned ANDReg = createResultReg(&ARM64::GPR32spRegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM64::ANDWri),
ANDReg)
.addReg(SrcReg)
@ -788,7 +790,8 @@ bool ARM64FastISel::SelectBranch(const Instruction *I) {
CondReg = FastEmitInst_extractsubreg(MVT::i32, CondReg, /*Kill=*/true,
ARM64::sub_32);
unsigned ANDReg = createResultReg(&ARM64::GPR32RegClass);
MRI.constrainRegClass(CondReg, &ARM64::GPR32RegClass);
unsigned ANDReg = createResultReg(&ARM64::GPR32spRegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM64::ANDWri),
ANDReg)
.addReg(CondReg)
@ -1030,7 +1033,9 @@ bool ARM64FastISel::SelectSelect(const Instruction *I) {
if (FalseReg == 0)
return false;
unsigned ANDReg = createResultReg(&ARM64::GPR32RegClass);
MRI.constrainRegClass(CondReg, &ARM64::GPR32RegClass);
unsigned ANDReg = createResultReg(&ARM64::GPR32spRegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM64::ANDWri),
ANDReg)
.addReg(CondReg)
@ -1669,8 +1674,9 @@ bool ARM64FastISel::SelectTrunc(const Instruction *I) {
// Issue an extract_subreg to get the lower 32-bits.
unsigned Reg32 = FastEmitInst_extractsubreg(MVT::i32, SrcReg, /*Kill=*/true,
ARM64::sub_32);
MRI.constrainRegClass(Reg32, &ARM64::GPR32RegClass);
// Create the AND instruction which performs the actual truncation.
unsigned ANDReg = createResultReg(&ARM64::GPR32RegClass);
unsigned ANDReg = createResultReg(&ARM64::GPR32spRegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM64::ANDWri),
ANDReg)
.addReg(Reg32)
@ -1691,7 +1697,8 @@ unsigned ARM64FastISel::Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt) {
DestVT = MVT::i32;
if (isZExt) {
unsigned ResultReg = createResultReg(&ARM64::GPR32RegClass);
MRI.constrainRegClass(SrcReg, &ARM64::GPR32RegClass);
unsigned ResultReg = createResultReg(&ARM64::GPR32spRegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(ARM64::ANDWri),
ResultReg)
.addReg(SrcReg)

2
test/CodeGen/ARM64/fast-isel-fcmp.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
; RUN: llc < %s -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin | FileCheck %s
define zeroext i1 @fcmp_float1(float %a) nounwind ssp {
entry: