6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-09-24 23:28:41 +00:00
Code Issues Projects Releases Wiki Activity

Add stub methods for mips assembly matcher.

Browse Source 
Patch by Vladimir Medic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162124 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
2012-08-17 20:16:42 +00:00
parent 168843c013
commit 72e9b6aeb4
10 changed files with 106 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

68
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View File

@@ -11,11 +11,20 @@
#include "llvm/MC/MCParser/MCAsmLexer.h"
#include "llvm/MC/MCTargetAsmParser.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
#include "llvm/MC/MCTargetAsmParser.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/Support/MathExtras.h"
using namespace llvm;
namespace {
class MipsAsmParser : public MCTargetAsmParser {
#define GET_ASSEMBLER_HEADER
#include "MipsGenAsmMatcher.inc"
bool MatchAndEmitInstruction(SMLoc IDLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
MCStreamer &Out);
@@ -23,10 +32,11 @@ class MipsAsmParser : public MCTargetAsmParser {
bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
bool ParseInstruction(StringRef Name, SMLoc NameLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands);
SmallVectorImpl<MCParsedAsmOperand*> &Operands);
bool ParseDirective(AsmToken DirectiveID);
OperandMatchResultTy parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*>&);
public:
MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
: MCTargetAsmParser() {
@@ -35,6 +45,57 @@ public:
};
}
namespace {
/// MipsOperand - Instances of this class represent a parsed Mips machine
/// instruction.
class MipsOperand : public MCParsedAsmOperand {
enum KindTy {
k_CondCode,
k_CoprocNum,
k_Immediate,
k_Memory,
k_PostIndexRegister,
k_Register,
k_Token
} Kind;
MipsOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
public:
void addRegOperands(MCInst &Inst, unsigned N) const {
llvm_unreachable("unimplemented!");
}
void addExpr(MCInst &Inst, const MCExpr *Expr) const{
llvm_unreachable("unimplemented!");
}
void addImmOperands(MCInst &Inst, unsigned N) const {
llvm_unreachable("unimplemented!");
}
void addMemOperands(MCInst &Inst, unsigned N) const {
llvm_unreachable("unimplemented!");
}
bool isReg() const { return Kind == k_Register; }
bool isImm() const { return Kind == k_Immediate; }
bool isToken() const { return Kind == k_Token; }
bool isMem() const { return Kind == k_Memory; }
StringRef getToken() const {
assert(Kind == k_Token && "Invalid access!");
return "";
}
unsigned getReg() const {
assert((Kind == k_Register) && "Invalid access!");
return 0;
}
virtual void print(raw_ostream &OS) const {
llvm_unreachable("unimplemented!");
}
};
}
bool MipsAsmParser::
MatchAndEmitInstruction(SMLoc IDLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
@@ -58,6 +119,11 @@ ParseDirective(AsmToken DirectiveID) {
return true;
}
MipsAsmParser::OperandMatchResultTy MipsAsmParser::
parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*>&) {
return MatchOperand_ParseFail;
}
extern "C" void LLVMInitializeMipsAsmParser() {
RegisterMCAsmParser<MipsAsmParser> X(TheMipsTarget);
RegisterMCAsmParser<MipsAsmParser> Y(TheMipselTarget);