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Add support for the 'h' constraint.

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Part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134203 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2011-06-30 23:23:01 +00:00
parent 5cd2791513
commit 73744df0c4
3 changed files with 17 additions and 1 deletions
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8
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -7482,6 +7482,7 @@ ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
default: break;
case 'l': return C_RegisterClass;
case 'w': return C_RegisterClass;
case 'h': return C_RegisterClass;
}
} else if (Constraint.size() == 2) {
switch (Constraint[0]) {
@ -7534,11 +7535,16 @@ ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
if (Constraint.size() == 1) {
// GCC ARM Constraint Letters
switch (Constraint[0]) {
case 'l':
case 'l': // Low regs or general regs.
if (Subtarget->isThumb())
return Pair(0U, ARM::tGPRRegisterClass);
else
return Pair(0U, ARM::GPRRegisterClass);
case 'h': // High regs or no regs.
if (Subtarget->isThumb())
return Pair(0U, ARM::hGPRRegisterClass);
else
return Pair(0u, static_cast<const TargetRegisterClass*>(0));
case 'r':
return Pair(0U, ARM::GPRRegisterClass);
case 'w':

3
lib/Target/ARM/ARMRegisterInfo.td
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@ -228,6 +228,9 @@ def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> {
// the general GPR register class above (MOV, e.g.)
def tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)>;
// The high registers in thumb mode, R8-R15.
def hGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, tGPR)>;
// For tail calls, we can't use callee-saved registers, as they are restored
// to the saved value before the tail call, which would clobber a call address.
// Note, getMinimalPhysRegClass(R0) returns tGPR because of the names of

7
test/CodeGen/Thumb/inlineasm-thumb.ll Normal file
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@ -0,0 +1,7 @@
; RUN: llc < %s -march=thumb | FileCheck %s
define i32 @t1(i32 %x, i32 %y) nounwind {
entry:
; CHECK: mov r0, r12
%0 = tail call i32 asm "mov $0, $1", "=l,h"(i32 %y) nounwind
ret i32 %0
}