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[mips] [IAS] Do not generate redundant move when expanding lw/sw with symbol.

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Summary:
Even though there is no 2nd register operand in the "lw/sw $8, symbol" case, we still try to find one, 
and we end up with $0, which makes us generate an unnecessary "addu $8, $8, $0" (a.k.a. "move $8, $8").

We can avoid this by checking if the 2nd register operand is different from $0, before generating the addu.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8055

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234406 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Toma Tabacu
2015-04-08 13:52:41 +00:00
parent f1f0734f14
commit 739ca842aa
2 changed files with 22 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
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@@ -2078,12 +2078,14 @@ void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc,
// Prepare TempInst for next instruction.
TempInst.clear();
// Add temp register to base.
TempInst.setOpcode(Mips::ADDu);
TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
TempInst.addOperand(MCOperand::CreateReg(BaseRegNum));
Instructions.push_back(TempInst);
TempInst.clear();
if (BaseRegNum != Mips::ZERO) {
TempInst.setOpcode(Mips::ADDu);
TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
TempInst.addOperand(MCOperand::CreateReg(BaseRegNum));
Instructions.push_back(TempInst);
TempInst.clear();
}
// And finally, create original instruction with low part
// of offset and new base.
TempInst.setOpcode(Inst.getOpcode());