mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-30 17:33:24 +00:00
Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc
into XXXGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133922 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
4ef4c171db
commit
73f50d9bc3
@ -25,7 +25,8 @@
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// Defines symbolic names for ARM registers. This defines a mapping from
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// register name to register number.
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//
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#include "ARMGenRegisterNames.inc"
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#define GET_REGINFO_ENUM
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#include "ARMGenRegisterInfo.inc"
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// Defines symbolic names for the ARM instructions.
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//
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@ -39,7 +39,9 @@
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Support/CommandLine.h"
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#include "ARMGenRegisterDesc.inc"
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#define GET_REGINFO_MC_DESC
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#define GET_REGINFO_TARGET_DESC
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#include "ARMGenRegisterInfo.inc"
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using namespace llvm;
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@ -16,7 +16,9 @@
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#include "ARM.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "ARMGenRegisterInfo.h.inc"
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#define GET_REGINFO_HEADER
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#include "ARMGenRegisterInfo.inc"
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namespace llvm {
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class ARMSubtarget;
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@ -1,8 +1,5 @@
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set(LLVM_TARGET_DEFINITIONS ARM.td)
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tablegen(ARMGenRegisterNames.inc -gen-register-enums)
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tablegen(ARMGenRegisterDesc.inc -gen-register-desc)
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tablegen(ARMGenRegisterInfo.h.inc -gen-register-info-header)
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tablegen(ARMGenRegisterInfo.inc -gen-register-info)
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tablegen(ARMGenInstrNames.inc -gen-instr-enums)
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tablegen(ARMGenInstrInfo.inc -gen-instr-desc)
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@ -12,8 +12,7 @@ LIBRARYNAME = LLVMARMCodeGen
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TARGET = ARM
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# Make sure that tblgen is run, first thing.
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BUILT_SOURCES = ARMGenRegisterNames.inc ARMGenRegisterDesc.inc \
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ARMGenRegisterInfo.h.inc ARMGenRegisterInfo.inc \
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BUILT_SOURCES = ARMGenRegisterInfo.inc \
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ARMGenInstrNames.inc ARMGenInstrInfo.inc \
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ARMGenAsmWriter.inc ARMGenAsmMatcher.inc \
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ARMGenDAGISel.inc ARMGenSubtarget.inc \
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@ -44,7 +44,9 @@ namespace llvm {
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// Defines symbolic names for Alpha registers. This defines a mapping from
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// register name to register number.
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//
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#include "AlphaGenRegisterNames.inc"
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#define GET_REGINFO_ENUM
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#include "AlphaGenRegisterInfo.inc"
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// Defines symbolic names for the Alpha instructions.
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//
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@ -33,8 +33,11 @@
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include <cstdlib>
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#include "AlphaGenRegisterDesc.inc"
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#define GET_REGINFO_MC_DESC
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#define GET_REGINFO_TARGET_DESC
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#include "AlphaGenRegisterInfo.inc"
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using namespace llvm;
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AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
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@ -15,7 +15,9 @@
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#define ALPHAREGISTERINFO_H
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "AlphaGenRegisterInfo.h.inc"
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#define GET_REGINFO_HEADER
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#include "AlphaGenRegisterInfo.inc"
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namespace llvm {
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@ -1,8 +1,5 @@
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set(LLVM_TARGET_DEFINITIONS Alpha.td)
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tablegen(AlphaGenRegisterNames.inc -gen-register-enums)
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tablegen(AlphaGenRegisterDesc.inc -gen-register-desc)
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tablegen(AlphaGenRegisterInfo.h.inc -gen-register-info-header)
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tablegen(AlphaGenRegisterInfo.inc -gen-register-info)
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tablegen(AlphaGenInstrNames.inc -gen-instr-enums)
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tablegen(AlphaGenInstrInfo.inc -gen-instr-desc)
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@ -12,8 +12,7 @@ LIBRARYNAME = LLVMAlphaCodeGen
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TARGET = Alpha
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# Make sure that tblgen is run, first thing.
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BUILT_SOURCES = AlphaGenRegisterNames.inc AlphaGenRegisterDesc.inc \
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AlphaGenRegisterInfo.h.inc AlphaGenRegisterInfo.inc \
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BUILT_SOURCES = AlphaGenRegisterInfo.inc \
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AlphaGenInstrNames.inc AlphaGenInstrInfo.inc \
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AlphaGenAsmWriter.inc AlphaGenDAGISel.inc \
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AlphaGenCallingConv.inc AlphaGenSubtarget.inc
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@ -30,7 +30,8 @@ namespace llvm {
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// Defines symbolic names for Blackfin registers. This defines a mapping from
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// register name to register number.
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#include "BlackfinGenRegisterNames.inc"
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#define GET_REGINFO_ENUM
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#include "BlackfinGenRegisterInfo.inc"
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// Defines symbolic names for the Blackfin instructions.
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#include "BlackfinGenInstrNames.inc"
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@ -29,8 +29,11 @@
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#include "llvm/Type.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "BlackfinGenRegisterDesc.inc"
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#define GET_REGINFO_MC_DESC
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#define GET_REGINFO_TARGET_DESC
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#include "BlackfinGenRegisterInfo.inc"
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using namespace llvm;
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BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st,
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@ -16,7 +16,9 @@
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#define BLACKFINREGISTERINFO_H
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "BlackfinGenRegisterInfo.h.inc"
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#define GET_REGINFO_HEADER
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#include "BlackfinGenRegisterInfo.inc"
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namespace llvm {
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@ -1,8 +1,5 @@
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set(LLVM_TARGET_DEFINITIONS Blackfin.td)
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tablegen(BlackfinGenRegisterNames.inc -gen-register-enums)
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tablegen(BlackfinGenRegisterDesc.inc -gen-register-desc)
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tablegen(BlackfinGenRegisterInfo.h.inc -gen-register-info-header)
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tablegen(BlackfinGenRegisterInfo.inc -gen-register-info)
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tablegen(BlackfinGenInstrNames.inc -gen-instr-enums)
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tablegen(BlackfinGenInstrInfo.inc -gen-instr-desc)
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@ -12,9 +12,7 @@ LIBRARYNAME = LLVMBlackfinCodeGen
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TARGET = Blackfin
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# Make sure that tblgen is run, first thing.
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BUILT_SOURCES = BlackfinGenRegisterNames.inc BlackfinGenRegisterDesc.inc \
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BlackfinGenRegisterInfo.h.inc BlackfinGenRegisterInfo.inc \
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BlackfinGenInstrNames.inc \
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BUILT_SOURCES = BlackfinGenRegisterInfo.inc BlackfinGenInstrNames.inc \
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BlackfinGenInstrInfo.inc BlackfinGenAsmWriter.inc \
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BlackfinGenDAGISel.inc BlackfinGenSubtarget.inc \
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BlackfinGenCallingConv.inc BlackfinGenIntrinsics.inc
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@ -1,11 +1,8 @@
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set(LLVM_TARGET_DEFINITIONS SPU.td)
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tablegen(SPUGenInstrNames.inc -gen-instr-enums)
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tablegen(SPUGenRegisterNames.inc -gen-register-enums)
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tablegen(SPUGenAsmWriter.inc -gen-asm-writer)
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tablegen(SPUGenCodeEmitter.inc -gen-emitter)
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tablegen(SPUGenRegisterDesc.inc -gen-register-desc)
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tablegen(SPUGenRegisterInfo.h.inc -gen-register-info-header)
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tablegen(SPUGenRegisterInfo.inc -gen-register-info)
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tablegen(SPUGenInstrInfo.inc -gen-instr-desc)
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tablegen(SPUGenDAGISel.inc -gen-dag-isel)
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@ -10,10 +10,8 @@
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LEVEL = ../../..
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LIBRARYNAME = LLVMCellSPUCodeGen
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TARGET = SPU
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BUILT_SOURCES = SPUGenInstrNames.inc \
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BUILT_SOURCES = SPUGenInstrNames.inc SPUGenRegisterInfo.inc \
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SPUGenAsmWriter.inc SPUGenCodeEmitter.inc \
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SPUGenRegisterNames.inc SPUGenRegisterDesc.inc \
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SPUGenRegisterInfo.h.inc SPUGenRegisterInfo.inc \
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SPUGenInstrInfo.inc SPUGenDAGISel.inc \
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SPUGenSubtarget.inc SPUGenCallingConv.inc
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@ -42,7 +42,9 @@
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include <cstdlib>
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#include "SPUGenRegisterDesc.inc"
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#define GET_REGINFO_MC_DESC
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#define GET_REGINFO_TARGET_DESC
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#include "SPUGenRegisterInfo.inc"
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using namespace llvm;
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@ -16,7 +16,9 @@
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#define SPU_REGISTERINFO_H
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#include "SPU.h"
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#include "SPUGenRegisterInfo.h.inc"
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#define GET_REGINFO_HEADER
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#include "SPUGenRegisterInfo.inc"
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namespace llvm {
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class SPUSubtarget;
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@ -13,6 +13,7 @@
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// Define symbolic names for Cell registers. This defines a mapping from
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// register name to register number.
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//
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#include "SPUGenRegisterNames.inc"
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#define GET_REGINFO_ENUM
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#include "SPUGenRegisterInfo.inc"
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#endif
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@ -1,9 +1,6 @@
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set(LLVM_TARGET_DEFINITIONS MBlaze.td)
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tablegen(MBlazeGenRegisterNames.inc -gen-register-enums)
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tablegen(MBlazeGenRegisterDesc.inc -gen-register-desc)
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tablegen(MBlazeGenRegisterInfo.h.inc -gen-register-info-header)
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tablegen(MBlazeGenRegisterInfo.inc -gen-register-info)
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tablegen(MBlazeGenInstrNames.inc -gen-instr-enums)
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tablegen(MBlazeGenInstrInfo.inc -gen-instr-desc)
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tablegen(MBlazeGenCodeEmitter.inc -gen-emitter)
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@ -39,7 +39,8 @@ namespace llvm {
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// Defines symbolic names for MBlaze registers. This defines a mapping from
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// register name to register number.
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#include "MBlazeGenRegisterNames.inc"
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#define GET_REGINFO_ENUM
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#include "MBlazeGenRegisterInfo.inc"
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// Defines symbolic names for the MBlaze instructions.
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#include "MBlazeGenInstrNames.inc"
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@ -36,8 +36,11 @@
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "MBlazeGenRegisterDesc.inc"
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#define GET_REGINFO_MC_DESC
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#define GET_REGINFO_TARGET_DESC
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#include "MBlazeGenRegisterInfo.inc"
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using namespace llvm;
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MBlazeRegisterInfo::
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@ -17,7 +17,9 @@
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#include "MBlaze.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "MBlazeGenRegisterInfo.h.inc"
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#define GET_REGINFO_HEADER
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#include "MBlazeGenRegisterInfo.inc"
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namespace llvm {
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class MBlazeSubtarget;
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@ -11,9 +11,7 @@ LIBRARYNAME = LLVMMBlazeCodeGen
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TARGET = MBlaze
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# Make sure that tblgen is run, first thing.
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BUILT_SOURCES = MBlazeGenRegisterInfo.h.inc MBlazeGenRegisterNames.inc \
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MBlazeGenRegisterInfo.inc MBlazeGenRegisterDesc.inc \
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MBlazeGenInstrNames.inc \
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BUILT_SOURCES = MBlazeGenRegisterInfo.inc MBlazeGenInstrNames.inc \
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MBlazeGenInstrInfo.inc MBlazeGenAsmWriter.inc \
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MBlazeGenDAGISel.inc MBlazeGenAsmMatcher.inc \
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MBlazeGenCodeEmitter.inc MBlazeGenCallingConv.inc \
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@ -1,8 +1,5 @@
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set(LLVM_TARGET_DEFINITIONS MSP430.td)
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tablegen(MSP430GenRegisterNames.inc -gen-register-enums)
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tablegen(MSP430GenRegisterDesc.inc -gen-register-desc)
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tablegen(MSP430GenRegisterInfo.h.inc -gen-register-info-header)
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tablegen(MSP430GenRegisterInfo.inc -gen-register-info)
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tablegen(MSP430GenInstrNames.inc -gen-instr-enums)
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tablegen(MSP430GenInstrInfo.inc -gen-instr-desc)
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@ -47,7 +47,8 @@ namespace llvm {
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// Defines symbolic names for MSP430 registers.
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// This defines a mapping from register name to register number.
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#include "MSP430GenRegisterNames.inc"
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#define GET_REGINFO_ENUM
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#include "MSP430GenRegisterInfo.inc"
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// Defines symbolic names for the MSP430 instructions.
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#include "MSP430GenInstrNames.inc"
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@ -25,7 +25,9 @@
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "MSP430GenRegisterDesc.inc"
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#define GET_REGINFO_MC_DESC
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#define GET_REGINFO_TARGET_DESC
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#include "MSP430GenRegisterInfo.inc"
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using namespace llvm;
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@ -15,7 +15,9 @@
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#define LLVM_TARGET_MSP430REGISTERINFO_H
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "MSP430GenRegisterInfo.h.inc"
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#define GET_REGINFO_HEADER
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#include "MSP430GenRegisterInfo.inc"
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namespace llvm {
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@ -12,9 +12,7 @@ LIBRARYNAME = LLVMMSP430CodeGen
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TARGET = MSP430
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# Make sure that tblgen is run, first thing.
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BUILT_SOURCES = MSP430GenRegisterInfo.h.inc MSP430GenRegisterNames.inc \
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MSP430GenRegisterInfo.inc MSP430GenRegisterDesc.inc \
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MSP430GenInstrNames.inc \
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BUILT_SOURCES = MSP430GenRegisterInfo.inc MSP430GenInstrNames.inc \
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MSP430GenInstrInfo.inc MSP430GenAsmWriter.inc \
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MSP430GenDAGISel.inc MSP430GenCallingConv.inc \
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MSP430GenSubtarget.inc
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@ -1,8 +1,5 @@
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set(LLVM_TARGET_DEFINITIONS Mips.td)
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tablegen(MipsGenRegisterNames.inc -gen-register-enums)
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tablegen(MipsGenRegisterDesc.inc -gen-register-desc)
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tablegen(MipsGenRegisterInfo.h.inc -gen-register-info-header)
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tablegen(MipsGenRegisterInfo.inc -gen-register-info)
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tablegen(MipsGenInstrNames.inc -gen-instr-enums)
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tablegen(MipsGenInstrInfo.inc -gen-instr-desc)
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@ -12,9 +12,7 @@ LIBRARYNAME = LLVMMipsCodeGen
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TARGET = Mips
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# Make sure that tblgen is run, first thing.
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BUILT_SOURCES = MipsGenRegisterInfo.h.inc MipsGenRegisterNames.inc \
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MipsGenRegisterInfo.inc MipsGenRegisterDesc.inc \
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MipsGenInstrNames.inc \
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BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrNames.inc \
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MipsGenInstrInfo.inc MipsGenAsmWriter.inc \
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MipsGenDAGISel.inc MipsGenCallingConv.inc \
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MipsGenSubtarget.inc
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@ -35,7 +35,8 @@ namespace llvm {
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// Defines symbolic names for Mips registers. This defines a mapping from
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// register name to register number.
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#include "MipsGenRegisterNames.inc"
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#define GET_REGINFO_ENUM
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#include "MipsGenRegisterInfo.inc"
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// Defines symbolic names for the Mips instructions.
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#include "MipsGenInstrNames.inc"
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@ -35,7 +35,9 @@
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "MipsGenRegisterDesc.inc"
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#define GET_REGINFO_MC_DESC
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#define GET_REGINFO_TARGET_DESC
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#include "MipsGenRegisterInfo.inc"
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using namespace llvm;
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@ -16,7 +16,9 @@
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#include "Mips.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "MipsGenRegisterInfo.h.inc"
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#define GET_REGINFO_HEADER
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#include "MipsGenRegisterInfo.inc"
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namespace llvm {
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class MipsSubtarget;
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@ -5,10 +5,7 @@ tablegen(PTXGenCallingConv.inc -gen-callingconv)
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tablegen(PTXGenDAGISel.inc -gen-dag-isel)
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tablegen(PTXGenInstrInfo.inc -gen-instr-desc)
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tablegen(PTXGenInstrNames.inc -gen-instr-enums)
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tablegen(PTXGenRegisterDesc.inc -gen-register-desc)
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tablegen(PTXGenRegisterInfo.inc -gen-register-info)
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tablegen(PTXGenRegisterInfo.h.inc -gen-register-info-header)
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tablegen(PTXGenRegisterNames.inc -gen-register-enums)
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tablegen(PTXGenSubtarget.inc -gen-subtarget)
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add_llvm_target(PTXCodeGen
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@ -17,10 +17,7 @@ BUILT_SOURCES = PTXGenAsmWriter.inc \
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PTXGenDAGISel.inc \
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PTXGenInstrInfo.inc \
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PTXGenInstrNames.inc \
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PTXGenRegisterDesc.inc \
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PTXGenRegisterInfo.inc \
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PTXGenRegisterInfo.h.inc \
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PTXGenRegisterNames.inc \
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PTXGenSubtarget.inc
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DIRS = TargetInfo
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@ -47,7 +47,8 @@ namespace llvm {
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} // namespace llvm;
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// Defines symbolic names for PTX registers.
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#include "PTXGenRegisterNames.inc"
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#define GET_REGINFO_ENUM
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#include "PTXGenRegisterInfo.inc"
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// Defines symbolic names for the PTX instructions.
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#include "PTXGenInstrNames.inc"
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@ -17,11 +17,11 @@
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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||||
using namespace llvm;
|
||||
|
||||
#include "PTXGenRegisterDesc.inc"
|
||||
#define GET_REGINFO_MC_DESC
|
||||
#define GET_REGINFO_TARGET_DESC
|
||||
#include "PTXGenRegisterInfo.inc"
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
PTXRegisterInfo::PTXRegisterInfo(PTXTargetMachine &TM,
|
||||
const TargetInstrInfo &TII)
|
||||
|
||||
@ -17,7 +17,8 @@
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include "llvm/ADT/BitVector.h"
|
||||
|
||||
#include "PTXGenRegisterInfo.h.inc"
|
||||
#define GET_REGINFO_HEADER
|
||||
#include "PTXGenRegisterInfo.inc"
|
||||
|
||||
namespace llvm {
|
||||
class PTXTargetMachine;
|
||||
|
||||
@ -1,12 +1,9 @@
|
||||
set(LLVM_TARGET_DEFINITIONS PPC.td)
|
||||
|
||||
tablegen(PPCGenInstrNames.inc -gen-instr-enums)
|
||||
tablegen(PPCGenRegisterNames.inc -gen-register-enums)
|
||||
tablegen(PPCGenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(PPCGenCodeEmitter.inc -gen-emitter)
|
||||
tablegen(PPCGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
|
||||
tablegen(PPCGenRegisterDesc.inc -gen-register-desc)
|
||||
tablegen(PPCGenRegisterInfo.h.inc -gen-register-info-header)
|
||||
tablegen(PPCGenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(PPCGenInstrInfo.inc -gen-instr-desc)
|
||||
tablegen(PPCGenDAGISel.inc -gen-dag-isel)
|
||||
|
||||
@ -12,10 +12,8 @@ LIBRARYNAME = LLVMPowerPCCodeGen
|
||||
TARGET = PPC
|
||||
|
||||
# Make sure that tblgen is run, first thing.
|
||||
BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterNames.inc \
|
||||
BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterInfo.inc \
|
||||
PPCGenAsmWriter.inc PPCGenCodeEmitter.inc \
|
||||
PPCGenRegisterDesc.inc \
|
||||
PPCGenRegisterInfo.h.inc PPCGenRegisterInfo.inc \
|
||||
PPCGenInstrInfo.inc PPCGenDAGISel.inc \
|
||||
PPCGenSubtarget.inc PPCGenCallingConv.inc \
|
||||
PPCGenMCCodeEmitter.inc
|
||||
|
||||
@ -84,7 +84,8 @@ namespace llvm {
|
||||
// Defines symbolic names for PowerPC registers. This defines a mapping from
|
||||
// register name to register number.
|
||||
//
|
||||
#include "PPCGenRegisterNames.inc"
|
||||
#define GET_REGINFO_ENUM
|
||||
#include "PPCGenRegisterInfo.inc"
|
||||
|
||||
// Defines symbolic names for the PowerPC instructions.
|
||||
//
|
||||
|
||||
@ -43,7 +43,9 @@
|
||||
#include "llvm/ADT/BitVector.h"
|
||||
#include "llvm/ADT/STLExtras.h"
|
||||
#include <cstdlib>
|
||||
#include "PPCGenRegisterDesc.inc"
|
||||
|
||||
#define GET_REGINFO_MC_DESC
|
||||
#define GET_REGINFO_TARGET_DESC
|
||||
#include "PPCGenRegisterInfo.inc"
|
||||
|
||||
// FIXME (64-bit): Eventually enable by default.
|
||||
|
||||
@ -16,9 +16,11 @@
|
||||
#define POWERPC32_REGISTERINFO_H
|
||||
|
||||
#include "PPC.h"
|
||||
#include "PPCGenRegisterInfo.h.inc"
|
||||
#include <map>
|
||||
|
||||
#define GET_REGINFO_HEADER
|
||||
#include "PPCGenRegisterInfo.inc"
|
||||
|
||||
namespace llvm {
|
||||
class PPCSubtarget;
|
||||
class TargetInstrInfo;
|
||||
|
||||
@ -1,8 +1,5 @@
|
||||
set(LLVM_TARGET_DEFINITIONS Sparc.td)
|
||||
|
||||
tablegen(SparcGenRegisterNames.inc -gen-register-enums)
|
||||
tablegen(SparcGenRegisterDesc.inc -gen-register-desc)
|
||||
tablegen(SparcGenRegisterInfo.h.inc -gen-register-info-header)
|
||||
tablegen(SparcGenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(SparcGenInstrNames.inc -gen-instr-enums)
|
||||
tablegen(SparcGenInstrInfo.inc -gen-instr-desc)
|
||||
|
||||
@ -12,9 +12,7 @@ LIBRARYNAME = LLVMSparcCodeGen
|
||||
TARGET = Sparc
|
||||
|
||||
# Make sure that tblgen is run, first thing.
|
||||
BUILT_SOURCES = SparcGenRegisterInfo.h.inc SparcGenRegisterNames.inc \
|
||||
SparcGenRegisterInfo.inc SparcGenRegisterDesc.inc \
|
||||
SparcGenInstrNames.inc \
|
||||
BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrNames.inc \
|
||||
SparcGenInstrInfo.inc SparcGenAsmWriter.inc \
|
||||
SparcGenDAGISel.inc SparcGenSubtarget.inc SparcGenCallingConv.inc
|
||||
|
||||
|
||||
@ -36,7 +36,8 @@ namespace llvm {
|
||||
// Defines symbolic names for Sparc registers. This defines a mapping from
|
||||
// register name to register number.
|
||||
//
|
||||
#include "SparcGenRegisterNames.inc"
|
||||
#define GET_REGINFO_ENUM
|
||||
#include "SparcGenRegisterInfo.inc"
|
||||
|
||||
// Defines symbolic names for the Sparc instructions.
|
||||
//
|
||||
|
||||
@ -23,8 +23,11 @@
|
||||
#include "llvm/Type.h"
|
||||
#include "llvm/ADT/BitVector.h"
|
||||
#include "llvm/ADT/STLExtras.h"
|
||||
#include "SparcGenRegisterDesc.inc"
|
||||
|
||||
#define GET_REGINFO_MC_DESC
|
||||
#define GET_REGINFO_TARGET_DESC
|
||||
#include "SparcGenRegisterInfo.inc"
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
|
||||
|
||||
@ -15,7 +15,9 @@
|
||||
#define SPARCREGISTERINFO_H
|
||||
|
||||
#include "llvm/Target/TargetRegisterInfo.h"
|
||||
#include "SparcGenRegisterInfo.h.inc"
|
||||
|
||||
#define GET_REGINFO_HEADER
|
||||
#include "SparcGenRegisterInfo.inc"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
|
||||
@ -1,8 +1,5 @@
|
||||
set(LLVM_TARGET_DEFINITIONS SystemZ.td)
|
||||
|
||||
tablegen(SystemZGenRegisterNames.inc -gen-register-enums)
|
||||
tablegen(SystemZGenRegisterDesc.inc -gen-register-desc)
|
||||
tablegen(SystemZGenRegisterInfo.h.inc -gen-register-info-header)
|
||||
tablegen(SystemZGenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(SystemZGenInstrNames.inc -gen-instr-enums)
|
||||
tablegen(SystemZGenInstrInfo.inc -gen-instr-desc)
|
||||
|
||||
@ -12,9 +12,7 @@ LIBRARYNAME = LLVMSystemZCodeGen
|
||||
TARGET = SystemZ
|
||||
|
||||
# Make sure that tblgen is run, first thing.
|
||||
BUILT_SOURCES = SystemZGenRegisterInfo.h.inc SystemZGenRegisterNames.inc \
|
||||
SystemZGenRegisterInfo.inc SystemZGenRegisterDesc.inc \
|
||||
SystemZGenInstrNames.inc \
|
||||
BUILT_SOURCES = SystemZGenRegisterInfo.inc SystemZGenInstrNames.inc \
|
||||
SystemZGenInstrInfo.inc SystemZGenAsmWriter.inc \
|
||||
SystemZGenDAGISel.inc SystemZGenSubtarget.inc SystemZGenCallingConv.inc
|
||||
|
||||
|
||||
@ -53,7 +53,8 @@ namespace llvm {
|
||||
|
||||
// Defines symbolic names for SystemZ registers.
|
||||
// This defines a mapping from register name to register number.
|
||||
#include "SystemZGenRegisterNames.inc"
|
||||
#define GET_REGINFO_ENUM
|
||||
#include "SystemZGenRegisterInfo.inc"
|
||||
|
||||
// Defines symbolic names for the SystemZ instructions.
|
||||
#include "SystemZGenInstrNames.inc"
|
||||
|
||||
@ -25,8 +25,11 @@
|
||||
#include "llvm/Target/TargetMachine.h"
|
||||
#include "llvm/Target/TargetOptions.h"
|
||||
#include "llvm/ADT/BitVector.h"
|
||||
#include "SystemZGenRegisterDesc.inc"
|
||||
|
||||
#define GET_REGINFO_MC_DESC
|
||||
#define GET_REGINFO_TARGET_DESC
|
||||
#include "SystemZGenRegisterInfo.inc"
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm,
|
||||
|
||||
@ -15,7 +15,9 @@
|
||||
#define SystemZREGISTERINFO_H
|
||||
|
||||
#include "llvm/Target/TargetRegisterInfo.h"
|
||||
#include "SystemZGenRegisterInfo.h.inc"
|
||||
|
||||
#define GET_REGINFO_HEADER
|
||||
#include "SystemZGenRegisterInfo.inc"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
|
||||
@ -1,8 +1,5 @@
|
||||
set(LLVM_TARGET_DEFINITIONS X86.td)
|
||||
|
||||
tablegen(X86GenRegisterNames.inc -gen-register-enums)
|
||||
tablegen(X86GenRegisterDesc.inc -gen-register-desc)
|
||||
tablegen(X86GenRegisterInfo.h.inc -gen-register-info-header)
|
||||
tablegen(X86GenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(X86GenDisassemblerTables.inc -gen-disassembler)
|
||||
tablegen(X86GenInstrNames.inc -gen-instr-enums)
|
||||
|
||||
@ -26,7 +26,8 @@
|
||||
#include "llvm/Support/MemoryObject.h"
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
|
||||
#include "X86GenRegisterNames.inc"
|
||||
#define GET_REGINFO_ENUM
|
||||
#include "X86GenRegisterInfo.inc"
|
||||
#include "X86GenEDInfo.inc"
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
@ -27,12 +27,11 @@
|
||||
using namespace llvm;
|
||||
|
||||
// Include the auto-generated portion of the assembly writer.
|
||||
#define GET_REGINFO_ENUM
|
||||
#include "X86GenRegisterInfo.inc"
|
||||
#define GET_INSTRUCTION_NAME
|
||||
#define PRINT_ALIAS_INSTR
|
||||
#include "X86GenRegisterNames.inc"
|
||||
#include "X86GenAsmWriter.inc"
|
||||
#undef PRINT_ALIAS_INSTR
|
||||
#undef GET_INSTRUCTION_NAME
|
||||
|
||||
X86ATTInstPrinter::X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI)
|
||||
: MCInstPrinter(MAI) {
|
||||
|
||||
@ -14,7 +14,9 @@
|
||||
#include "X86TargetDesc.h"
|
||||
#include "llvm/MC/MCRegisterInfo.h"
|
||||
#include "llvm/Target/TargetRegistry.h"
|
||||
#include "X86GenRegisterDesc.inc"
|
||||
|
||||
#define GET_REGINFO_MC_DESC
|
||||
#include "X86GenRegisterInfo.inc"
|
||||
using namespace llvm;
|
||||
|
||||
MCRegisterInfo *createX86MCRegisterInfo() {
|
||||
|
||||
@ -23,6 +23,7 @@ extern Target TheX86_32Target, TheX86_64Target;
|
||||
// Defines symbolic names for X86 registers. This defines a mapping from
|
||||
// register name to register number.
|
||||
//
|
||||
#include "X86GenRegisterNames.inc"
|
||||
#define GET_REGINFO_ENUM
|
||||
#include "X86GenRegisterInfo.inc"
|
||||
|
||||
#endif
|
||||
|
||||
@ -12,8 +12,7 @@ LIBRARYNAME = LLVMX86CodeGen
|
||||
TARGET = X86
|
||||
|
||||
# Make sure that tblgen is run, first thing.
|
||||
BUILT_SOURCES = X86GenRegisterNames.inc X86GenRegisterDesc.inc \
|
||||
X86GenRegisterInfo.h.inc X86GenRegisterInfo.inc \
|
||||
BUILT_SOURCES = X86GenRegisterInfo.inc \
|
||||
X86GenInstrNames.inc X86GenInstrInfo.inc \
|
||||
X86GenAsmWriter.inc X86GenAsmMatcher.inc \
|
||||
X86GenAsmWriter1.inc X86GenDAGISel.inc \
|
||||
|
||||
@ -39,8 +39,11 @@
|
||||
#include "llvm/ADT/STLExtras.h"
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include "llvm/Support/CommandLine.h"
|
||||
#include "X86GenRegisterDesc.inc"
|
||||
|
||||
#define GET_REGINFO_MC_DESC
|
||||
#define GET_REGINFO_TARGET_DESC
|
||||
#include "X86GenRegisterInfo.inc"
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
cl::opt<bool>
|
||||
|
||||
@ -15,7 +15,9 @@
|
||||
#define X86REGISTERINFO_H
|
||||
|
||||
#include "llvm/Target/TargetRegisterInfo.h"
|
||||
#include "X86GenRegisterInfo.h.inc"
|
||||
|
||||
#define GET_REGINFO_HEADER
|
||||
#include "X86GenRegisterInfo.inc"
|
||||
|
||||
namespace llvm {
|
||||
class Type;
|
||||
|
||||
@ -1,8 +1,5 @@
|
||||
set(LLVM_TARGET_DEFINITIONS XCore.td)
|
||||
|
||||
tablegen(XCoreGenRegisterNames.inc -gen-register-enums)
|
||||
tablegen(XCoreGenRegisterDesc.inc -gen-register-desc)
|
||||
tablegen(XCoreGenRegisterInfo.h.inc -gen-register-info-header)
|
||||
tablegen(XCoreGenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(XCoreGenInstrNames.inc -gen-instr-enums)
|
||||
tablegen(XCoreGenInstrInfo.inc -gen-instr-desc)
|
||||
|
||||
@ -12,9 +12,7 @@ LIBRARYNAME = LLVMXCoreCodeGen
|
||||
TARGET = XCore
|
||||
|
||||
# Make sure that tblgen is run, first thing.
|
||||
BUILT_SOURCES = XCoreGenRegisterInfo.h.inc XCoreGenRegisterNames.inc \
|
||||
XCoreGenRegisterInfo.inc XCoreGenRegisterDesc.inc \
|
||||
XCoreGenInstrNames.inc \
|
||||
BUILT_SOURCES = XCoreGenRegisterInfo.inc XCoreGenInstrNames.inc \
|
||||
XCoreGenInstrInfo.inc XCoreGenAsmWriter.inc \
|
||||
XCoreGenDAGISel.inc XCoreGenCallingConv.inc \
|
||||
XCoreGenSubtarget.inc
|
||||
|
||||
@ -32,7 +32,8 @@ namespace llvm {
|
||||
// Defines symbolic names for XCore registers. This defines a mapping from
|
||||
// register name to register number.
|
||||
//
|
||||
#include "XCoreGenRegisterNames.inc"
|
||||
#define GET_REGINFO_ENUM
|
||||
#include "XCoreGenRegisterInfo.inc"
|
||||
|
||||
// Defines symbolic names for the XCore instructions.
|
||||
//
|
||||
|
||||
@ -32,8 +32,11 @@
|
||||
#include "llvm/Support/Debug.h"
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
#include "XCoreGenRegisterDesc.inc"
|
||||
|
||||
#define GET_REGINFO_MC_DESC
|
||||
#define GET_REGINFO_TARGET_DESC
|
||||
#include "XCoreGenRegisterInfo.inc"
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
|
||||
|
||||
@ -15,7 +15,9 @@
|
||||
#define XCOREREGISTERINFO_H
|
||||
|
||||
#include "llvm/Target/TargetRegisterInfo.h"
|
||||
#include "XCoreGenRegisterInfo.h.inc"
|
||||
|
||||
#define GET_REGINFO_HEADER
|
||||
#include "XCoreGenRegisterInfo.inc"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
|
||||
@ -25,14 +25,18 @@
|
||||
using namespace llvm;
|
||||
|
||||
// runEnums - Print out enum values for all of the registers.
|
||||
void RegisterInfoEmitter::runEnums(raw_ostream &OS) {
|
||||
CodeGenTarget Target(Records);
|
||||
CodeGenRegBank &Bank = Target.getRegBank();
|
||||
void
|
||||
RegisterInfoEmitter::runEnums(raw_ostream &OS,
|
||||
CodeGenTarget &Target, CodeGenRegBank &Bank) {
|
||||
const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
|
||||
|
||||
std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
|
||||
|
||||
EmitSourceFileHeader("Target Register Enum Values", OS);
|
||||
|
||||
OS << "\n#ifdef GET_REGINFO_ENUM\n";
|
||||
OS << "#undef GET_REGINFO_ENUM\n";
|
||||
|
||||
OS << "namespace llvm {\n\n";
|
||||
|
||||
if (!Namespace.empty())
|
||||
@ -63,12 +67,33 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS) {
|
||||
if (!Namespace.empty())
|
||||
OS << "}\n";
|
||||
}
|
||||
|
||||
const std::vector<CodeGenRegisterClass> &RegisterClasses =
|
||||
Target.getRegisterClasses();
|
||||
|
||||
if (!RegisterClasses.empty()) {
|
||||
OS << "\n// Register classes\n";
|
||||
OS << "namespace " << RegisterClasses[0].Namespace << " {\n";
|
||||
OS << "enum {\n";
|
||||
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
|
||||
if (i) OS << ",\n";
|
||||
OS << " " << RegisterClasses[i].getName() << "RegClassID";
|
||||
OS << " = " << i;
|
||||
}
|
||||
OS << "\n };\n";
|
||||
OS << "}\n";
|
||||
}
|
||||
|
||||
OS << "} // End llvm namespace \n";
|
||||
OS << "#endif // GET_REGINFO_ENUM\n\n";
|
||||
}
|
||||
|
||||
void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
|
||||
void RegisterInfoEmitter::runHeader(raw_ostream &OS, CodeGenTarget &Target) {
|
||||
EmitSourceFileHeader("Register Information Header Fragment", OS);
|
||||
CodeGenTarget Target(Records);
|
||||
|
||||
OS << "\n#ifdef GET_REGINFO_HEADER\n";
|
||||
OS << "#undef GET_REGINFO_HEADER\n";
|
||||
|
||||
const std::string &TargetName = Target.getName();
|
||||
std::string ClassName = TargetName + "GenRegisterInfo";
|
||||
|
||||
@ -100,14 +125,6 @@ void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
|
||||
OS << "namespace " << RegisterClasses[0].Namespace
|
||||
<< " { // Register classes\n";
|
||||
|
||||
OS << " enum {\n";
|
||||
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
|
||||
if (i) OS << ",\n";
|
||||
OS << " " << RegisterClasses[i].getName() << "RegClassID";
|
||||
OS << " = " << i;
|
||||
}
|
||||
OS << "\n };\n\n";
|
||||
|
||||
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
|
||||
const CodeGenRegisterClass &RC = RegisterClasses[i];
|
||||
const std::string &Name = RC.getName();
|
||||
@ -129,17 +146,125 @@ void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
|
||||
OS << "} // end of namespace " << TargetName << "\n\n";
|
||||
}
|
||||
OS << "} // End llvm namespace \n";
|
||||
OS << "#endif // GET_REGINFO_HEADER\n\n";
|
||||
}
|
||||
|
||||
//
|
||||
// RegisterInfoEmitter::run - Main register file description emitter.
|
||||
// runMCDesc - Print out MC register descriptions.
|
||||
//
|
||||
void RegisterInfoEmitter::run(raw_ostream &OS) {
|
||||
CodeGenTarget Target(Records);
|
||||
CodeGenRegBank &RegBank = Target.getRegBank();
|
||||
RegBank.computeDerivedInfo();
|
||||
void
|
||||
RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
|
||||
CodeGenRegBank &RegBank) {
|
||||
EmitSourceFileHeader("MC Register Information", OS);
|
||||
|
||||
EmitSourceFileHeader("Register Information Source Fragment", OS);
|
||||
OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
|
||||
OS << "#undef GET_REGINFO_MC_DESC\n";
|
||||
|
||||
std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
|
||||
RegBank.computeOverlaps(Overlaps);
|
||||
|
||||
OS << "namespace llvm {\n\n";
|
||||
|
||||
const std::string &TargetName = Target.getName();
|
||||
std::string ClassName = TargetName + "GenMCRegisterInfo";
|
||||
OS << "struct " << ClassName << " : public MCRegisterInfo {\n"
|
||||
<< " explicit " << ClassName << "(const MCRegisterDesc *D);\n";
|
||||
OS << "};\n";
|
||||
|
||||
OS << "\nnamespace {\n";
|
||||
|
||||
const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
|
||||
|
||||
// Emit an overlap list for all registers.
|
||||
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
|
||||
const CodeGenRegister *Reg = Regs[i];
|
||||
const CodeGenRegister::Set &O = Overlaps[Reg];
|
||||
// Move Reg to the front so TRI::getAliasSet can share the list.
|
||||
OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { "
|
||||
<< getQualifiedName(Reg->TheDef) << ", ";
|
||||
for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
|
||||
I != E; ++I)
|
||||
if (*I != Reg)
|
||||
OS << getQualifiedName((*I)->TheDef) << ", ";
|
||||
OS << "0 };\n";
|
||||
}
|
||||
|
||||
// Emit the empty sub-registers list
|
||||
OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
|
||||
// Loop over all of the registers which have sub-registers, emitting the
|
||||
// sub-registers list to memory.
|
||||
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
|
||||
const CodeGenRegister &Reg = *Regs[i];
|
||||
if (Reg.getSubRegs().empty())
|
||||
continue;
|
||||
// getSubRegs() orders by SubRegIndex. We want a topological order.
|
||||
SetVector<CodeGenRegister*> SR;
|
||||
Reg.addSubRegsPreOrder(SR);
|
||||
OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
|
||||
for (unsigned j = 0, je = SR.size(); j != je; ++j)
|
||||
OS << getQualifiedName(SR[j]->TheDef) << ", ";
|
||||
OS << "0 };\n";
|
||||
}
|
||||
|
||||
// Emit the empty super-registers list
|
||||
OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
|
||||
// Loop over all of the registers which have super-registers, emitting the
|
||||
// super-registers list to memory.
|
||||
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
|
||||
const CodeGenRegister &Reg = *Regs[i];
|
||||
const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
|
||||
if (SR.empty())
|
||||
continue;
|
||||
OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { ";
|
||||
for (unsigned j = 0, je = SR.size(); j != je; ++j)
|
||||
OS << getQualifiedName(SR[j]->TheDef) << ", ";
|
||||
OS << "0 };\n";
|
||||
}
|
||||
|
||||
OS << "\n const MCRegisterDesc " << TargetName
|
||||
<< "RegDesc[] = { // Descriptors\n";
|
||||
OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
|
||||
|
||||
// Now that register alias and sub-registers sets have been emitted, emit the
|
||||
// register descriptors now.
|
||||
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
|
||||
const CodeGenRegister &Reg = *Regs[i];
|
||||
OS << " { \"";
|
||||
OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
|
||||
if (!Reg.getSubRegs().empty())
|
||||
OS << Reg.getName() << "_SubRegsSet,\t";
|
||||
else
|
||||
OS << "Empty_SubRegsSet,\t";
|
||||
if (!Reg.getSuperRegs().empty())
|
||||
OS << Reg.getName() << "_SuperRegsSet";
|
||||
else
|
||||
OS << "Empty_SuperRegsSet";
|
||||
OS << " },\n";
|
||||
}
|
||||
OS << " };\n"; // End of register descriptors...
|
||||
|
||||
OS << "}\n\n"; // End of anonymous namespace...
|
||||
|
||||
// MCRegisterInfo initialization routine.
|
||||
OS << "static inline void Init" << TargetName
|
||||
<< "MCRegisterInfo(MCRegisterInfo *RI) {\n";
|
||||
OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
|
||||
<< Regs.size()+1 << ");\n}\n\n";
|
||||
|
||||
OS << "} // End llvm namespace \n";
|
||||
OS << "#endif // GET_REGINFO_MC_DESC\n\n";
|
||||
}
|
||||
|
||||
//
|
||||
// runTargetDesc - Output the target register and register file descriptions.
|
||||
//
|
||||
void
|
||||
RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
|
||||
CodeGenRegBank &RegBank){
|
||||
EmitSourceFileHeader("Target Register and Register Classes Information", OS);
|
||||
|
||||
OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
|
||||
OS << "#undef GET_REGINFO_TARGET_DESC\n";
|
||||
|
||||
OS << "namespace llvm {\n\n";
|
||||
|
||||
@ -614,102 +739,16 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
|
||||
OS << " };\n}\n\n";
|
||||
|
||||
OS << "} // End llvm namespace \n";
|
||||
OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
|
||||
}
|
||||
|
||||
void RegisterInfoEmitter::runDesc(raw_ostream &OS) {
|
||||
void RegisterInfoEmitter::run(raw_ostream &OS) {
|
||||
CodeGenTarget Target(Records);
|
||||
CodeGenRegBank &RegBank = Target.getRegBank();
|
||||
RegBank.computeDerivedInfo();
|
||||
std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
|
||||
RegBank.computeOverlaps(Overlaps);
|
||||
|
||||
OS << "namespace llvm {\n\n";
|
||||
|
||||
const std::string &TargetName = Target.getName();
|
||||
std::string ClassName = TargetName + "GenMCRegisterInfo";
|
||||
OS << "struct " << ClassName << " : public MCRegisterInfo {\n"
|
||||
<< " explicit " << ClassName << "(const MCRegisterDesc *D);\n";
|
||||
OS << "};\n";
|
||||
|
||||
OS << "\nnamespace {\n";
|
||||
|
||||
const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
|
||||
|
||||
// Emit an overlap list for all registers.
|
||||
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
|
||||
const CodeGenRegister *Reg = Regs[i];
|
||||
const CodeGenRegister::Set &O = Overlaps[Reg];
|
||||
// Move Reg to the front so TRI::getAliasSet can share the list.
|
||||
OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { "
|
||||
<< getQualifiedName(Reg->TheDef) << ", ";
|
||||
for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
|
||||
I != E; ++I)
|
||||
if (*I != Reg)
|
||||
OS << getQualifiedName((*I)->TheDef) << ", ";
|
||||
OS << "0 };\n";
|
||||
}
|
||||
|
||||
// Emit the empty sub-registers list
|
||||
OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
|
||||
// Loop over all of the registers which have sub-registers, emitting the
|
||||
// sub-registers list to memory.
|
||||
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
|
||||
const CodeGenRegister &Reg = *Regs[i];
|
||||
if (Reg.getSubRegs().empty())
|
||||
continue;
|
||||
// getSubRegs() orders by SubRegIndex. We want a topological order.
|
||||
SetVector<CodeGenRegister*> SR;
|
||||
Reg.addSubRegsPreOrder(SR);
|
||||
OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
|
||||
for (unsigned j = 0, je = SR.size(); j != je; ++j)
|
||||
OS << getQualifiedName(SR[j]->TheDef) << ", ";
|
||||
OS << "0 };\n";
|
||||
}
|
||||
|
||||
// Emit the empty super-registers list
|
||||
OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
|
||||
// Loop over all of the registers which have super-registers, emitting the
|
||||
// super-registers list to memory.
|
||||
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
|
||||
const CodeGenRegister &Reg = *Regs[i];
|
||||
const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
|
||||
if (SR.empty())
|
||||
continue;
|
||||
OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { ";
|
||||
for (unsigned j = 0, je = SR.size(); j != je; ++j)
|
||||
OS << getQualifiedName(SR[j]->TheDef) << ", ";
|
||||
OS << "0 };\n";
|
||||
}
|
||||
|
||||
OS << "\n const MCRegisterDesc " << TargetName
|
||||
<< "RegDesc[] = { // Descriptors\n";
|
||||
OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
|
||||
|
||||
// Now that register alias and sub-registers sets have been emitted, emit the
|
||||
// register descriptors now.
|
||||
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
|
||||
const CodeGenRegister &Reg = *Regs[i];
|
||||
OS << " { \"";
|
||||
OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
|
||||
if (!Reg.getSubRegs().empty())
|
||||
OS << Reg.getName() << "_SubRegsSet,\t";
|
||||
else
|
||||
OS << "Empty_SubRegsSet,\t";
|
||||
if (!Reg.getSuperRegs().empty())
|
||||
OS << Reg.getName() << "_SuperRegsSet";
|
||||
else
|
||||
OS << "Empty_SuperRegsSet";
|
||||
OS << " },\n";
|
||||
}
|
||||
OS << " };\n"; // End of register descriptors...
|
||||
|
||||
OS << "}\n\n"; // End of anonymous namespace...
|
||||
|
||||
// MCRegisterInfo initialization routine.
|
||||
OS << "static inline void Init" << TargetName
|
||||
<< "MCRegisterInfo(MCRegisterInfo *RI) {\n";
|
||||
OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
|
||||
<< Regs.size()+1 << ");\n}\n\n";
|
||||
|
||||
OS << "} // End llvm namespace \n";
|
||||
runEnums(OS, Target, RegBank);
|
||||
runHeader(OS, Target);
|
||||
runMCDesc(OS, Target, RegBank);
|
||||
runTargetDesc(OS, Target, RegBank);
|
||||
}
|
||||
|
||||
@ -20,22 +20,28 @@
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class CodeGenRegBank;
|
||||
class CodeGenTarget;
|
||||
|
||||
class RegisterInfoEmitter : public TableGenBackend {
|
||||
RecordKeeper &Records;
|
||||
public:
|
||||
RegisterInfoEmitter(RecordKeeper &R) : Records(R) {}
|
||||
|
||||
// run - Output the register file description, returning true on failure.
|
||||
void run(raw_ostream &o);
|
||||
// runEnums - Print out enum values for all of the registers.
|
||||
void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
|
||||
|
||||
// runHeader - Emit a header fragment for the register info emitter.
|
||||
void runHeader(raw_ostream &o);
|
||||
void runHeader(raw_ostream &o, CodeGenTarget &Target);
|
||||
|
||||
// runEnums - Print out enum values for all of the registers.
|
||||
void runEnums(raw_ostream &o);
|
||||
// runMCDesc - Print out MC register descriptions.
|
||||
void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
|
||||
|
||||
// runDesc - Print out register descriptions.
|
||||
void runDesc(raw_ostream &o);
|
||||
// runTargetDesc - Output the target register and register file descriptions.
|
||||
void runTargetDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
|
||||
|
||||
// run - Output the register file description.
|
||||
void run(raw_ostream &o);
|
||||
};
|
||||
|
||||
} // End llvm namespace
|
||||
|
||||
@ -54,7 +54,7 @@ using namespace llvm;
|
||||
enum ActionType {
|
||||
PrintRecords,
|
||||
GenEmitter,
|
||||
GenRegisterEnums, GenRegisterDesc, GenRegisterInfo, GenRegisterInfoHeader,
|
||||
GenRegisterInfo,
|
||||
GenInstrEnums, GenInstrs, GenAsmWriter, GenAsmMatcher,
|
||||
GenARMDecoder,
|
||||
GenDisassembler,
|
||||
@ -93,14 +93,8 @@ namespace {
|
||||
"Print all records to stdout (default)"),
|
||||
clEnumValN(GenEmitter, "gen-emitter",
|
||||
"Generate machine code emitter"),
|
||||
clEnumValN(GenRegisterEnums, "gen-register-enums",
|
||||
"Generate enum values for registers"),
|
||||
clEnumValN(GenRegisterDesc, "gen-register-desc",
|
||||
"Generate register descriptions"),
|
||||
clEnumValN(GenRegisterInfo, "gen-register-info",
|
||||
"Generate registers & reg-classes info"),
|
||||
clEnumValN(GenRegisterInfoHeader, "gen-register-info-header",
|
||||
"Generate registers & reg-classes info header"),
|
||||
"Generate registers and register classes info"),
|
||||
clEnumValN(GenInstrEnums, "gen-instr-enums",
|
||||
"Generate enum values for instructions"),
|
||||
clEnumValN(GenInstrs, "gen-instr-desc",
|
||||
@ -263,18 +257,9 @@ int main(int argc, char **argv) {
|
||||
case GenEmitter:
|
||||
CodeEmitterGen(Records).run(Out.os());
|
||||
break;
|
||||
case GenRegisterEnums:
|
||||
RegisterInfoEmitter(Records).runEnums(Out.os());
|
||||
break;
|
||||
case GenRegisterDesc:
|
||||
RegisterInfoEmitter(Records).runDesc(Out.os());
|
||||
break;
|
||||
case GenRegisterInfo:
|
||||
RegisterInfoEmitter(Records).run(Out.os());
|
||||
break;
|
||||
case GenRegisterInfoHeader:
|
||||
RegisterInfoEmitter(Records).runHeader(Out.os());
|
||||
break;
|
||||
case GenInstrEnums:
|
||||
InstrEnumEmitter(Records).run(Out.os());
|
||||
break;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user