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Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc

Browse Source 
into XXXGenRegisterInfo.inc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133922 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2011-06-27 18:32:37 +00:00
parent 4ef4c171db
commit 73f50d9bc3
71 changed files with 295 additions and 256 deletions
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3
lib/Target/ARM/ARMBaseInfo.h
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@ -25,7 +25,8 @@
// Defines symbolic names for ARM registers. This defines a mapping from // Defines symbolic names for ARM registers. This defines a mapping from
// register name to register number. // register name to register number.
// //
#include "ARMGenRegisterNames.inc" #define GET_REGINFO_ENUM
#include "ARMGenRegisterInfo.inc"
// Defines symbolic names for the ARM instructions. // Defines symbolic names for the ARM instructions.
// //

4
lib/Target/ARM/ARMBaseRegisterInfo.cpp
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@ -39,7 +39,9 @@
#include "llvm/ADT/BitVector.h" #include "llvm/ADT/BitVector.h"
#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/SmallVector.h"
#include "llvm/Support/CommandLine.h" #include "llvm/Support/CommandLine.h"
#include "ARMGenRegisterDesc.inc"
#define GET_REGINFO_MC_DESC
#define GET_REGINFO_TARGET_DESC
#include "ARMGenRegisterInfo.inc" #include "ARMGenRegisterInfo.inc"
using namespace llvm; using namespace llvm;

4
lib/Target/ARM/ARMBaseRegisterInfo.h
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@ -16,7 +16,9 @@
#include "ARM.h" #include "ARM.h"
#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetRegisterInfo.h"
#include "ARMGenRegisterInfo.h.inc"
#define GET_REGINFO_HEADER
#include "ARMGenRegisterInfo.inc"
namespace llvm { namespace llvm {
class ARMSubtarget; class ARMSubtarget;

3
lib/Target/ARM/CMakeLists.txt
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@ -1,8 +1,5 @@
set(LLVM_TARGET_DEFINITIONS ARM.td) set(LLVM_TARGET_DEFINITIONS ARM.td)
tablegen(ARMGenRegisterNames.inc -gen-register-enums)
tablegen(ARMGenRegisterDesc.inc -gen-register-desc)
tablegen(ARMGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(ARMGenRegisterInfo.inc -gen-register-info) tablegen(ARMGenRegisterInfo.inc -gen-register-info)
tablegen(ARMGenInstrNames.inc -gen-instr-enums) tablegen(ARMGenInstrNames.inc -gen-instr-enums)
tablegen(ARMGenInstrInfo.inc -gen-instr-desc) tablegen(ARMGenInstrInfo.inc -gen-instr-desc)

3
lib/Target/ARM/Makefile
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@ -12,8 +12,7 @@ LIBRARYNAME = LLVMARMCodeGen
TARGET = ARM TARGET = ARM
# Make sure that tblgen is run, first thing. # Make sure that tblgen is run, first thing.
BUILT_SOURCES = ARMGenRegisterNames.inc ARMGenRegisterDesc.inc \ BUILT_SOURCES = ARMGenRegisterInfo.inc \
ARMGenRegisterInfo.h.inc ARMGenRegisterInfo.inc \
ARMGenInstrNames.inc ARMGenInstrInfo.inc \ ARMGenInstrNames.inc ARMGenInstrInfo.inc \
ARMGenAsmWriter.inc ARMGenAsmMatcher.inc \ ARMGenAsmWriter.inc ARMGenAsmMatcher.inc \
ARMGenDAGISel.inc ARMGenSubtarget.inc \ ARMGenDAGISel.inc ARMGenSubtarget.inc \

4
lib/Target/Alpha/Alpha.h
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@ -44,7 +44,9 @@ namespace llvm {
// Defines symbolic names for Alpha registers. This defines a mapping from // Defines symbolic names for Alpha registers. This defines a mapping from
// register name to register number. // register name to register number.
// //
#include "AlphaGenRegisterNames.inc"
#define GET_REGINFO_ENUM
#include "AlphaGenRegisterInfo.inc"
// Defines symbolic names for the Alpha instructions. // Defines symbolic names for the Alpha instructions.
// //

5
lib/Target/Alpha/AlphaRegisterInfo.cpp
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@ -33,8 +33,11 @@
#include "llvm/ADT/BitVector.h" #include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/STLExtras.h"
#include <cstdlib> #include <cstdlib>
#include "AlphaGenRegisterDesc.inc"
#define GET_REGINFO_MC_DESC
#define GET_REGINFO_TARGET_DESC
#include "AlphaGenRegisterInfo.inc" #include "AlphaGenRegisterInfo.inc"
using namespace llvm; using namespace llvm;
AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii) AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)

4
lib/Target/Alpha/AlphaRegisterInfo.h
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@ -15,7 +15,9 @@
#define ALPHAREGISTERINFO_H #define ALPHAREGISTERINFO_H
#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetRegisterInfo.h"
#include "AlphaGenRegisterInfo.h.inc"
#define GET_REGINFO_HEADER
#include "AlphaGenRegisterInfo.inc"
namespace llvm { namespace llvm {

3
lib/Target/Alpha/CMakeLists.txt
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@ -1,8 +1,5 @@
set(LLVM_TARGET_DEFINITIONS Alpha.td) set(LLVM_TARGET_DEFINITIONS Alpha.td)
tablegen(AlphaGenRegisterNames.inc -gen-register-enums)
tablegen(AlphaGenRegisterDesc.inc -gen-register-desc)
tablegen(AlphaGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(AlphaGenRegisterInfo.inc -gen-register-info) tablegen(AlphaGenRegisterInfo.inc -gen-register-info)
tablegen(AlphaGenInstrNames.inc -gen-instr-enums) tablegen(AlphaGenInstrNames.inc -gen-instr-enums)
tablegen(AlphaGenInstrInfo.inc -gen-instr-desc) tablegen(AlphaGenInstrInfo.inc -gen-instr-desc)

3
lib/Target/Alpha/Makefile
View File

@ -12,8 +12,7 @@ LIBRARYNAME = LLVMAlphaCodeGen
TARGET = Alpha TARGET = Alpha
# Make sure that tblgen is run, first thing. # Make sure that tblgen is run, first thing.
BUILT_SOURCES = AlphaGenRegisterNames.inc AlphaGenRegisterDesc.inc \ BUILT_SOURCES = AlphaGenRegisterInfo.inc \
AlphaGenRegisterInfo.h.inc AlphaGenRegisterInfo.inc \
AlphaGenInstrNames.inc AlphaGenInstrInfo.inc \ AlphaGenInstrNames.inc AlphaGenInstrInfo.inc \
AlphaGenAsmWriter.inc AlphaGenDAGISel.inc \ AlphaGenAsmWriter.inc AlphaGenDAGISel.inc \
AlphaGenCallingConv.inc AlphaGenSubtarget.inc AlphaGenCallingConv.inc AlphaGenSubtarget.inc

3
lib/Target/Blackfin/Blackfin.h
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@ -30,7 +30,8 @@ namespace llvm {
// Defines symbolic names for Blackfin registers. This defines a mapping from // Defines symbolic names for Blackfin registers. This defines a mapping from
// register name to register number. // register name to register number.
#include "BlackfinGenRegisterNames.inc" #define GET_REGINFO_ENUM
#include "BlackfinGenRegisterInfo.inc"
// Defines symbolic names for the Blackfin instructions. // Defines symbolic names for the Blackfin instructions.
#include "BlackfinGenInstrNames.inc" #include "BlackfinGenInstrNames.inc"

5
lib/Target/Blackfin/BlackfinRegisterInfo.cpp
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@ -29,8 +29,11 @@
#include "llvm/Type.h" #include "llvm/Type.h"
#include "llvm/ADT/BitVector.h" #include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/STLExtras.h"
#include "BlackfinGenRegisterDesc.inc"
#define GET_REGINFO_MC_DESC
#define GET_REGINFO_TARGET_DESC
#include "BlackfinGenRegisterInfo.inc" #include "BlackfinGenRegisterInfo.inc"
using namespace llvm; using namespace llvm;
BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st, BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st,

4
lib/Target/Blackfin/BlackfinRegisterInfo.h
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@ -16,7 +16,9 @@
#define BLACKFINREGISTERINFO_H #define BLACKFINREGISTERINFO_H
#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetRegisterInfo.h"
#include "BlackfinGenRegisterInfo.h.inc"
#define GET_REGINFO_HEADER
#include "BlackfinGenRegisterInfo.inc"
namespace llvm { namespace llvm {

3
lib/Target/Blackfin/CMakeLists.txt
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@ -1,8 +1,5 @@
set(LLVM_TARGET_DEFINITIONS Blackfin.td) set(LLVM_TARGET_DEFINITIONS Blackfin.td)
tablegen(BlackfinGenRegisterNames.inc -gen-register-enums)
tablegen(BlackfinGenRegisterDesc.inc -gen-register-desc)
tablegen(BlackfinGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(BlackfinGenRegisterInfo.inc -gen-register-info) tablegen(BlackfinGenRegisterInfo.inc -gen-register-info)
tablegen(BlackfinGenInstrNames.inc -gen-instr-enums) tablegen(BlackfinGenInstrNames.inc -gen-instr-enums)
tablegen(BlackfinGenInstrInfo.inc -gen-instr-desc) tablegen(BlackfinGenInstrInfo.inc -gen-instr-desc)

4
lib/Target/Blackfin/Makefile
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@ -12,9 +12,7 @@ LIBRARYNAME = LLVMBlackfinCodeGen
TARGET = Blackfin TARGET = Blackfin
# Make sure that tblgen is run, first thing. # Make sure that tblgen is run, first thing.
BUILT_SOURCES = BlackfinGenRegisterNames.inc BlackfinGenRegisterDesc.inc \ BUILT_SOURCES = BlackfinGenRegisterInfo.inc BlackfinGenInstrNames.inc \
BlackfinGenRegisterInfo.h.inc BlackfinGenRegisterInfo.inc \
BlackfinGenInstrNames.inc \
BlackfinGenInstrInfo.inc BlackfinGenAsmWriter.inc \ BlackfinGenInstrInfo.inc BlackfinGenAsmWriter.inc \
BlackfinGenDAGISel.inc BlackfinGenSubtarget.inc \ BlackfinGenDAGISel.inc BlackfinGenSubtarget.inc \
BlackfinGenCallingConv.inc BlackfinGenIntrinsics.inc BlackfinGenCallingConv.inc BlackfinGenIntrinsics.inc

3
lib/Target/CellSPU/CMakeLists.txt
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@ -1,11 +1,8 @@
set(LLVM_TARGET_DEFINITIONS SPU.td) set(LLVM_TARGET_DEFINITIONS SPU.td)
tablegen(SPUGenInstrNames.inc -gen-instr-enums) tablegen(SPUGenInstrNames.inc -gen-instr-enums)
tablegen(SPUGenRegisterNames.inc -gen-register-enums)
tablegen(SPUGenAsmWriter.inc -gen-asm-writer) tablegen(SPUGenAsmWriter.inc -gen-asm-writer)
tablegen(SPUGenCodeEmitter.inc -gen-emitter) tablegen(SPUGenCodeEmitter.inc -gen-emitter)
tablegen(SPUGenRegisterDesc.inc -gen-register-desc)
tablegen(SPUGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(SPUGenRegisterInfo.inc -gen-register-info) tablegen(SPUGenRegisterInfo.inc -gen-register-info)
tablegen(SPUGenInstrInfo.inc -gen-instr-desc) tablegen(SPUGenInstrInfo.inc -gen-instr-desc)
tablegen(SPUGenDAGISel.inc -gen-dag-isel) tablegen(SPUGenDAGISel.inc -gen-dag-isel)

4
lib/Target/CellSPU/Makefile
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@ -10,10 +10,8 @@
LEVEL = ../../.. LEVEL = ../../..
LIBRARYNAME = LLVMCellSPUCodeGen LIBRARYNAME = LLVMCellSPUCodeGen
TARGET = SPU TARGET = SPU
BUILT_SOURCES = SPUGenInstrNames.inc \ BUILT_SOURCES = SPUGenInstrNames.inc SPUGenRegisterInfo.inc \
SPUGenAsmWriter.inc SPUGenCodeEmitter.inc \ SPUGenAsmWriter.inc SPUGenCodeEmitter.inc \
SPUGenRegisterNames.inc SPUGenRegisterDesc.inc \
SPUGenRegisterInfo.h.inc SPUGenRegisterInfo.inc \
SPUGenInstrInfo.inc SPUGenDAGISel.inc \ SPUGenInstrInfo.inc SPUGenDAGISel.inc \
SPUGenSubtarget.inc SPUGenCallingConv.inc SPUGenSubtarget.inc SPUGenCallingConv.inc

4
lib/Target/CellSPU/SPURegisterInfo.cpp
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@ -42,7 +42,9 @@
#include "llvm/ADT/BitVector.h" #include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/STLExtras.h"
#include <cstdlib> #include <cstdlib>
#include "SPUGenRegisterDesc.inc"
#define GET_REGINFO_MC_DESC
#define GET_REGINFO_TARGET_DESC
#include "SPUGenRegisterInfo.inc" #include "SPUGenRegisterInfo.inc"
using namespace llvm; using namespace llvm;

4
lib/Target/CellSPU/SPURegisterInfo.h
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@ -16,7 +16,9 @@
#define SPU_REGISTERINFO_H #define SPU_REGISTERINFO_H
#include "SPU.h" #include "SPU.h"
#include "SPUGenRegisterInfo.h.inc"
#define GET_REGINFO_HEADER
#include "SPUGenRegisterInfo.inc"
namespace llvm { namespace llvm {
class SPUSubtarget; class SPUSubtarget;

3
lib/Target/CellSPU/SPURegisterNames.h
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@ -13,6 +13,7 @@
// Define symbolic names for Cell registers. This defines a mapping from // Define symbolic names for Cell registers. This defines a mapping from
// register name to register number. // register name to register number.
// //
#include "SPUGenRegisterNames.inc" #define GET_REGINFO_ENUM
#include "SPUGenRegisterInfo.inc"
#endif #endif

3
lib/Target/MBlaze/CMakeLists.txt
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@ -1,9 +1,6 @@
set(LLVM_TARGET_DEFINITIONS MBlaze.td) set(LLVM_TARGET_DEFINITIONS MBlaze.td)
tablegen(MBlazeGenRegisterNames.inc -gen-register-enums)
tablegen(MBlazeGenRegisterDesc.inc -gen-register-desc)
tablegen(MBlazeGenRegisterInfo.h.inc -gen-register-info-header) tablegen(MBlazeGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(MBlazeGenRegisterInfo.inc -gen-register-info)
tablegen(MBlazeGenInstrNames.inc -gen-instr-enums) tablegen(MBlazeGenInstrNames.inc -gen-instr-enums)
tablegen(MBlazeGenInstrInfo.inc -gen-instr-desc) tablegen(MBlazeGenInstrInfo.inc -gen-instr-desc)
tablegen(MBlazeGenCodeEmitter.inc -gen-emitter) tablegen(MBlazeGenCodeEmitter.inc -gen-emitter)

3
lib/Target/MBlaze/MBlaze.h
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@ -39,7 +39,8 @@ namespace llvm {
// Defines symbolic names for MBlaze registers. This defines a mapping from // Defines symbolic names for MBlaze registers. This defines a mapping from
// register name to register number. // register name to register number.
#include "MBlazeGenRegisterNames.inc" #define GET_REGINFO_ENUM
#include "MBlazeGenRegisterInfo.inc"
// Defines symbolic names for the MBlaze instructions. // Defines symbolic names for the MBlaze instructions.
#include "MBlazeGenInstrNames.inc" #include "MBlazeGenInstrNames.inc"

5
lib/Target/MBlaze/MBlazeRegisterInfo.cpp
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@ -36,8 +36,11 @@
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
#include "llvm/ADT/BitVector.h" #include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/STLExtras.h"
#include "MBlazeGenRegisterDesc.inc"
#define GET_REGINFO_MC_DESC
#define GET_REGINFO_TARGET_DESC
#include "MBlazeGenRegisterInfo.inc" #include "MBlazeGenRegisterInfo.inc"
using namespace llvm; using namespace llvm;
MBlazeRegisterInfo:: MBlazeRegisterInfo::

4
lib/Target/MBlaze/MBlazeRegisterInfo.h
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@ -17,7 +17,9 @@
#include "MBlaze.h" #include "MBlaze.h"
#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetRegisterInfo.h"
#include "MBlazeGenRegisterInfo.h.inc"
#define GET_REGINFO_HEADER
#include "MBlazeGenRegisterInfo.inc"
namespace llvm { namespace llvm {
class MBlazeSubtarget; class MBlazeSubtarget;

4
lib/Target/MBlaze/Makefile
View File

@ -11,9 +11,7 @@ LIBRARYNAME = LLVMMBlazeCodeGen
TARGET = MBlaze TARGET = MBlaze
# Make sure that tblgen is run, first thing. # Make sure that tblgen is run, first thing.
BUILT_SOURCES = MBlazeGenRegisterInfo.h.inc MBlazeGenRegisterNames.inc \ BUILT_SOURCES = MBlazeGenRegisterInfo.inc MBlazeGenInstrNames.inc \
MBlazeGenRegisterInfo.inc MBlazeGenRegisterDesc.inc \
MBlazeGenInstrNames.inc \
MBlazeGenInstrInfo.inc MBlazeGenAsmWriter.inc \ MBlazeGenInstrInfo.inc MBlazeGenAsmWriter.inc \
MBlazeGenDAGISel.inc MBlazeGenAsmMatcher.inc \ MBlazeGenDAGISel.inc MBlazeGenAsmMatcher.inc \
MBlazeGenCodeEmitter.inc MBlazeGenCallingConv.inc \ MBlazeGenCodeEmitter.inc MBlazeGenCallingConv.inc \

3
lib/Target/MSP430/CMakeLists.txt
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@ -1,8 +1,5 @@
set(LLVM_TARGET_DEFINITIONS MSP430.td) set(LLVM_TARGET_DEFINITIONS MSP430.td)
tablegen(MSP430GenRegisterNames.inc -gen-register-enums)
tablegen(MSP430GenRegisterDesc.inc -gen-register-desc)
tablegen(MSP430GenRegisterInfo.h.inc -gen-register-info-header)
tablegen(MSP430GenRegisterInfo.inc -gen-register-info) tablegen(MSP430GenRegisterInfo.inc -gen-register-info)
tablegen(MSP430GenInstrNames.inc -gen-instr-enums) tablegen(MSP430GenInstrNames.inc -gen-instr-enums)
tablegen(MSP430GenInstrInfo.inc -gen-instr-desc) tablegen(MSP430GenInstrInfo.inc -gen-instr-desc)

3
lib/Target/MSP430/MSP430.h
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@ -47,7 +47,8 @@ namespace llvm {
// Defines symbolic names for MSP430 registers. // Defines symbolic names for MSP430 registers.
// This defines a mapping from register name to register number. // This defines a mapping from register name to register number.
#include "MSP430GenRegisterNames.inc" #define GET_REGINFO_ENUM
#include "MSP430GenRegisterInfo.inc"
// Defines symbolic names for the MSP430 instructions. // Defines symbolic names for the MSP430 instructions.
#include "MSP430GenInstrNames.inc" #include "MSP430GenInstrNames.inc"

4
lib/Target/MSP430/MSP430RegisterInfo.cpp
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@ -25,7 +25,9 @@
#include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetOptions.h"
#include "llvm/ADT/BitVector.h" #include "llvm/ADT/BitVector.h"
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
#include "MSP430GenRegisterDesc.inc"
#define GET_REGINFO_MC_DESC
#define GET_REGINFO_TARGET_DESC
#include "MSP430GenRegisterInfo.inc" #include "MSP430GenRegisterInfo.inc"
using namespace llvm; using namespace llvm;

4
lib/Target/MSP430/MSP430RegisterInfo.h
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@ -15,7 +15,9 @@
#define LLVM_TARGET_MSP430REGISTERINFO_H #define LLVM_TARGET_MSP430REGISTERINFO_H
#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetRegisterInfo.h"
#include "MSP430GenRegisterInfo.h.inc"
#define GET_REGINFO_HEADER
#include "MSP430GenRegisterInfo.inc"
namespace llvm { namespace llvm {

4
lib/Target/MSP430/Makefile
View File

@ -12,9 +12,7 @@ LIBRARYNAME = LLVMMSP430CodeGen
TARGET = MSP430 TARGET = MSP430
# Make sure that tblgen is run, first thing. # Make sure that tblgen is run, first thing.
BUILT_SOURCES = MSP430GenRegisterInfo.h.inc MSP430GenRegisterNames.inc \ BUILT_SOURCES = MSP430GenRegisterInfo.inc MSP430GenInstrNames.inc \
MSP430GenRegisterInfo.inc MSP430GenRegisterDesc.inc \
MSP430GenInstrNames.inc \
MSP430GenInstrInfo.inc MSP430GenAsmWriter.inc \ MSP430GenInstrInfo.inc MSP430GenAsmWriter.inc \
MSP430GenDAGISel.inc MSP430GenCallingConv.inc \ MSP430GenDAGISel.inc MSP430GenCallingConv.inc \
MSP430GenSubtarget.inc MSP430GenSubtarget.inc

3
lib/Target/Mips/CMakeLists.txt
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@ -1,8 +1,5 @@
set(LLVM_TARGET_DEFINITIONS Mips.td) set(LLVM_TARGET_DEFINITIONS Mips.td)
tablegen(MipsGenRegisterNames.inc -gen-register-enums)
tablegen(MipsGenRegisterDesc.inc -gen-register-desc)
tablegen(MipsGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(MipsGenRegisterInfo.inc -gen-register-info) tablegen(MipsGenRegisterInfo.inc -gen-register-info)
tablegen(MipsGenInstrNames.inc -gen-instr-enums) tablegen(MipsGenInstrNames.inc -gen-instr-enums)
tablegen(MipsGenInstrInfo.inc -gen-instr-desc) tablegen(MipsGenInstrInfo.inc -gen-instr-desc)

4
lib/Target/Mips/Makefile
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@ -12,9 +12,7 @@ LIBRARYNAME = LLVMMipsCodeGen
TARGET = Mips TARGET = Mips
# Make sure that tblgen is run, first thing. # Make sure that tblgen is run, first thing.
BUILT_SOURCES = MipsGenRegisterInfo.h.inc MipsGenRegisterNames.inc \ BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrNames.inc \
MipsGenRegisterInfo.inc MipsGenRegisterDesc.inc \
MipsGenInstrNames.inc \
MipsGenInstrInfo.inc MipsGenAsmWriter.inc \ MipsGenInstrInfo.inc MipsGenAsmWriter.inc \
MipsGenDAGISel.inc MipsGenCallingConv.inc \ MipsGenDAGISel.inc MipsGenCallingConv.inc \
MipsGenSubtarget.inc MipsGenSubtarget.inc

3
lib/Target/Mips/Mips.h
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@ -35,7 +35,8 @@ namespace llvm {
// Defines symbolic names for Mips registers. This defines a mapping from // Defines symbolic names for Mips registers. This defines a mapping from
// register name to register number. // register name to register number.
#include "MipsGenRegisterNames.inc" #define GET_REGINFO_ENUM
#include "MipsGenRegisterInfo.inc"
// Defines symbolic names for the Mips instructions. // Defines symbolic names for the Mips instructions.
#include "MipsGenInstrNames.inc" #include "MipsGenInstrNames.inc"

4
lib/Target/Mips/MipsRegisterInfo.cpp
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@ -35,7 +35,9 @@
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
#include "llvm/ADT/BitVector.h" #include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/STLExtras.h"
#include "MipsGenRegisterDesc.inc"
#define GET_REGINFO_MC_DESC
#define GET_REGINFO_TARGET_DESC
#include "MipsGenRegisterInfo.inc" #include "MipsGenRegisterInfo.inc"
using namespace llvm; using namespace llvm;

4
lib/Target/Mips/MipsRegisterInfo.h
View File

@ -16,7 +16,9 @@
#include "Mips.h" #include "Mips.h"
#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetRegisterInfo.h"
#include "MipsGenRegisterInfo.h.inc"
#define GET_REGINFO_HEADER
#include "MipsGenRegisterInfo.inc"
namespace llvm { namespace llvm {
class MipsSubtarget; class MipsSubtarget;

3
lib/Target/PTX/CMakeLists.txt
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@ -5,10 +5,7 @@ tablegen(PTXGenCallingConv.inc -gen-callingconv)
tablegen(PTXGenDAGISel.inc -gen-dag-isel) tablegen(PTXGenDAGISel.inc -gen-dag-isel)
tablegen(PTXGenInstrInfo.inc -gen-instr-desc) tablegen(PTXGenInstrInfo.inc -gen-instr-desc)
tablegen(PTXGenInstrNames.inc -gen-instr-enums) tablegen(PTXGenInstrNames.inc -gen-instr-enums)
tablegen(PTXGenRegisterDesc.inc -gen-register-desc)
tablegen(PTXGenRegisterInfo.inc -gen-register-info) tablegen(PTXGenRegisterInfo.inc -gen-register-info)
tablegen(PTXGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(PTXGenRegisterNames.inc -gen-register-enums)
tablegen(PTXGenSubtarget.inc -gen-subtarget) tablegen(PTXGenSubtarget.inc -gen-subtarget)
add_llvm_target(PTXCodeGen add_llvm_target(PTXCodeGen

3
lib/Target/PTX/Makefile
View File

@ -17,10 +17,7 @@ BUILT_SOURCES = PTXGenAsmWriter.inc \
PTXGenDAGISel.inc \ PTXGenDAGISel.inc \
PTXGenInstrInfo.inc \ PTXGenInstrInfo.inc \
PTXGenInstrNames.inc \ PTXGenInstrNames.inc \
PTXGenRegisterDesc.inc \
PTXGenRegisterInfo.inc \ PTXGenRegisterInfo.inc \
PTXGenRegisterInfo.h.inc \
PTXGenRegisterNames.inc \
PTXGenSubtarget.inc PTXGenSubtarget.inc
DIRS = TargetInfo DIRS = TargetInfo

3
lib/Target/PTX/PTX.h
View File

@ -47,7 +47,8 @@ namespace llvm {
} // namespace llvm; } // namespace llvm;
// Defines symbolic names for PTX registers. // Defines symbolic names for PTX registers.
#include "PTXGenRegisterNames.inc" #define GET_REGINFO_ENUM
#include "PTXGenRegisterInfo.inc"
// Defines symbolic names for the PTX instructions. // Defines symbolic names for the PTX instructions.
#include "PTXGenInstrNames.inc" #include "PTXGenInstrNames.inc"

6
lib/Target/PTX/PTXRegisterInfo.cpp
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@ -17,11 +17,11 @@
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
using namespace llvm; #define GET_REGINFO_MC_DESC
#define GET_REGINFO_TARGET_DESC
#include "PTXGenRegisterDesc.inc"
#include "PTXGenRegisterInfo.inc" #include "PTXGenRegisterInfo.inc"
using namespace llvm;
PTXRegisterInfo::PTXRegisterInfo(PTXTargetMachine &TM, PTXRegisterInfo::PTXRegisterInfo(PTXTargetMachine &TM,
const TargetInstrInfo &TII) const TargetInstrInfo &TII)

3
lib/Target/PTX/PTXRegisterInfo.h
View File

@ -17,7 +17,8 @@
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
#include "llvm/ADT/BitVector.h" #include "llvm/ADT/BitVector.h"
#include "PTXGenRegisterInfo.h.inc" #define GET_REGINFO_HEADER
#include "PTXGenRegisterInfo.inc"
namespace llvm { namespace llvm {
class PTXTargetMachine; class PTXTargetMachine;

3
lib/Target/PowerPC/CMakeLists.txt
View File

@ -1,12 +1,9 @@
set(LLVM_TARGET_DEFINITIONS PPC.td) set(LLVM_TARGET_DEFINITIONS PPC.td)
tablegen(PPCGenInstrNames.inc -gen-instr-enums) tablegen(PPCGenInstrNames.inc -gen-instr-enums)
tablegen(PPCGenRegisterNames.inc -gen-register-enums)
tablegen(PPCGenAsmWriter.inc -gen-asm-writer) tablegen(PPCGenAsmWriter.inc -gen-asm-writer)
tablegen(PPCGenCodeEmitter.inc -gen-emitter) tablegen(PPCGenCodeEmitter.inc -gen-emitter)
tablegen(PPCGenMCCodeEmitter.inc -gen-emitter -mc-emitter) tablegen(PPCGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
tablegen(PPCGenRegisterDesc.inc -gen-register-desc)
tablegen(PPCGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(PPCGenRegisterInfo.inc -gen-register-info) tablegen(PPCGenRegisterInfo.inc -gen-register-info)
tablegen(PPCGenInstrInfo.inc -gen-instr-desc) tablegen(PPCGenInstrInfo.inc -gen-instr-desc)
tablegen(PPCGenDAGISel.inc -gen-dag-isel) tablegen(PPCGenDAGISel.inc -gen-dag-isel)

4
lib/Target/PowerPC/Makefile
View File

@ -12,10 +12,8 @@ LIBRARYNAME = LLVMPowerPCCodeGen
TARGET = PPC TARGET = PPC
# Make sure that tblgen is run, first thing. # Make sure that tblgen is run, first thing.
BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterNames.inc \ BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterInfo.inc \
PPCGenAsmWriter.inc PPCGenCodeEmitter.inc \ PPCGenAsmWriter.inc PPCGenCodeEmitter.inc \
PPCGenRegisterDesc.inc \
PPCGenRegisterInfo.h.inc PPCGenRegisterInfo.inc \
PPCGenInstrInfo.inc PPCGenDAGISel.inc \ PPCGenInstrInfo.inc PPCGenDAGISel.inc \
PPCGenSubtarget.inc PPCGenCallingConv.inc \ PPCGenSubtarget.inc PPCGenCallingConv.inc \
PPCGenMCCodeEmitter.inc PPCGenMCCodeEmitter.inc

3
lib/Target/PowerPC/PPC.h
View File

@ -84,7 +84,8 @@ namespace llvm {
// Defines symbolic names for PowerPC registers. This defines a mapping from // Defines symbolic names for PowerPC registers. This defines a mapping from
// register name to register number. // register name to register number.
// //
#include "PPCGenRegisterNames.inc" #define GET_REGINFO_ENUM
#include "PPCGenRegisterInfo.inc"
// Defines symbolic names for the PowerPC instructions. // Defines symbolic names for the PowerPC instructions.
// //

4
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -43,7 +43,9 @@
#include "llvm/ADT/BitVector.h" #include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/STLExtras.h"
#include <cstdlib> #include <cstdlib>
#include "PPCGenRegisterDesc.inc"
#define GET_REGINFO_MC_DESC
#define GET_REGINFO_TARGET_DESC
#include "PPCGenRegisterInfo.inc" #include "PPCGenRegisterInfo.inc"
// FIXME (64-bit): Eventually enable by default. // FIXME (64-bit): Eventually enable by default.

4
lib/Target/PowerPC/PPCRegisterInfo.h
View File

@ -16,9 +16,11 @@
#define POWERPC32_REGISTERINFO_H #define POWERPC32_REGISTERINFO_H
#include "PPC.h" #include "PPC.h"
#include "PPCGenRegisterInfo.h.inc"
#include <map> #include <map>
#define GET_REGINFO_HEADER
#include "PPCGenRegisterInfo.inc"
namespace llvm { namespace llvm {
class PPCSubtarget; class PPCSubtarget;
class TargetInstrInfo; class TargetInstrInfo;

3
lib/Target/Sparc/CMakeLists.txt
View File

@ -1,8 +1,5 @@
set(LLVM_TARGET_DEFINITIONS Sparc.td) set(LLVM_TARGET_DEFINITIONS Sparc.td)
tablegen(SparcGenRegisterNames.inc -gen-register-enums)
tablegen(SparcGenRegisterDesc.inc -gen-register-desc)
tablegen(SparcGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(SparcGenRegisterInfo.inc -gen-register-info) tablegen(SparcGenRegisterInfo.inc -gen-register-info)
tablegen(SparcGenInstrNames.inc -gen-instr-enums) tablegen(SparcGenInstrNames.inc -gen-instr-enums)
tablegen(SparcGenInstrInfo.inc -gen-instr-desc) tablegen(SparcGenInstrInfo.inc -gen-instr-desc)

4
lib/Target/Sparc/Makefile
View File

@ -12,9 +12,7 @@ LIBRARYNAME = LLVMSparcCodeGen
TARGET = Sparc TARGET = Sparc
# Make sure that tblgen is run, first thing. # Make sure that tblgen is run, first thing.
BUILT_SOURCES = SparcGenRegisterInfo.h.inc SparcGenRegisterNames.inc \ BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrNames.inc \
SparcGenRegisterInfo.inc SparcGenRegisterDesc.inc \
SparcGenInstrNames.inc \
SparcGenInstrInfo.inc SparcGenAsmWriter.inc \ SparcGenInstrInfo.inc SparcGenAsmWriter.inc \
SparcGenDAGISel.inc SparcGenSubtarget.inc SparcGenCallingConv.inc SparcGenDAGISel.inc SparcGenSubtarget.inc SparcGenCallingConv.inc

3
lib/Target/Sparc/Sparc.h
View File

@ -36,7 +36,8 @@ namespace llvm {
// Defines symbolic names for Sparc registers. This defines a mapping from // Defines symbolic names for Sparc registers. This defines a mapping from
// register name to register number. // register name to register number.
// //
#include "SparcGenRegisterNames.inc" #define GET_REGINFO_ENUM
#include "SparcGenRegisterInfo.inc"
// Defines symbolic names for the Sparc instructions. // Defines symbolic names for the Sparc instructions.
// //

5
lib/Target/Sparc/SparcRegisterInfo.cpp
View File

@ -23,8 +23,11 @@
#include "llvm/Type.h" #include "llvm/Type.h"
#include "llvm/ADT/BitVector.h" #include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/STLExtras.h"
#include "SparcGenRegisterDesc.inc"
#define GET_REGINFO_MC_DESC
#define GET_REGINFO_TARGET_DESC
#include "SparcGenRegisterInfo.inc" #include "SparcGenRegisterInfo.inc"
using namespace llvm; using namespace llvm;
SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st, SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,

4
lib/Target/Sparc/SparcRegisterInfo.h
View File

@ -15,7 +15,9 @@
#define SPARCREGISTERINFO_H #define SPARCREGISTERINFO_H
#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetRegisterInfo.h"
#include "SparcGenRegisterInfo.h.inc"
#define GET_REGINFO_HEADER
#include "SparcGenRegisterInfo.inc"
namespace llvm { namespace llvm {

3
lib/Target/SystemZ/CMakeLists.txt
View File

@ -1,8 +1,5 @@
set(LLVM_TARGET_DEFINITIONS SystemZ.td) set(LLVM_TARGET_DEFINITIONS SystemZ.td)
tablegen(SystemZGenRegisterNames.inc -gen-register-enums)
tablegen(SystemZGenRegisterDesc.inc -gen-register-desc)
tablegen(SystemZGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(SystemZGenRegisterInfo.inc -gen-register-info) tablegen(SystemZGenRegisterInfo.inc -gen-register-info)
tablegen(SystemZGenInstrNames.inc -gen-instr-enums) tablegen(SystemZGenInstrNames.inc -gen-instr-enums)
tablegen(SystemZGenInstrInfo.inc -gen-instr-desc) tablegen(SystemZGenInstrInfo.inc -gen-instr-desc)

4
lib/Target/SystemZ/Makefile
View File

@ -12,9 +12,7 @@ LIBRARYNAME = LLVMSystemZCodeGen
TARGET = SystemZ TARGET = SystemZ
# Make sure that tblgen is run, first thing. # Make sure that tblgen is run, first thing.
BUILT_SOURCES = SystemZGenRegisterInfo.h.inc SystemZGenRegisterNames.inc \ BUILT_SOURCES = SystemZGenRegisterInfo.inc SystemZGenInstrNames.inc \
SystemZGenRegisterInfo.inc SystemZGenRegisterDesc.inc \
SystemZGenInstrNames.inc \
SystemZGenInstrInfo.inc SystemZGenAsmWriter.inc \ SystemZGenInstrInfo.inc SystemZGenAsmWriter.inc \
SystemZGenDAGISel.inc SystemZGenSubtarget.inc SystemZGenCallingConv.inc SystemZGenDAGISel.inc SystemZGenSubtarget.inc SystemZGenCallingConv.inc

3
lib/Target/SystemZ/SystemZ.h
View File

@ -53,7 +53,8 @@ namespace llvm {
// Defines symbolic names for SystemZ registers. // Defines symbolic names for SystemZ registers.
// This defines a mapping from register name to register number. // This defines a mapping from register name to register number.
#include "SystemZGenRegisterNames.inc" #define GET_REGINFO_ENUM
#include "SystemZGenRegisterInfo.inc"
// Defines symbolic names for the SystemZ instructions. // Defines symbolic names for the SystemZ instructions.
#include "SystemZGenInstrNames.inc" #include "SystemZGenInstrNames.inc"

5
lib/Target/SystemZ/SystemZRegisterInfo.cpp
View File

@ -25,8 +25,11 @@
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetOptions.h"
#include "llvm/ADT/BitVector.h" #include "llvm/ADT/BitVector.h"
#include "SystemZGenRegisterDesc.inc"
#define GET_REGINFO_MC_DESC
#define GET_REGINFO_TARGET_DESC
#include "SystemZGenRegisterInfo.inc" #include "SystemZGenRegisterInfo.inc"
using namespace llvm; using namespace llvm;
SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm, SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm,

4
lib/Target/SystemZ/SystemZRegisterInfo.h
View File

@ -15,7 +15,9 @@
#define SystemZREGISTERINFO_H #define SystemZREGISTERINFO_H
#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetRegisterInfo.h"
#include "SystemZGenRegisterInfo.h.inc"
#define GET_REGINFO_HEADER
#include "SystemZGenRegisterInfo.inc"
namespace llvm { namespace llvm {

3
lib/Target/X86/CMakeLists.txt
View File

@ -1,8 +1,5 @@
set(LLVM_TARGET_DEFINITIONS X86.td) set(LLVM_TARGET_DEFINITIONS X86.td)
tablegen(X86GenRegisterNames.inc -gen-register-enums)
tablegen(X86GenRegisterDesc.inc -gen-register-desc)
tablegen(X86GenRegisterInfo.h.inc -gen-register-info-header)
tablegen(X86GenRegisterInfo.inc -gen-register-info) tablegen(X86GenRegisterInfo.inc -gen-register-info)
tablegen(X86GenDisassemblerTables.inc -gen-disassembler) tablegen(X86GenDisassemblerTables.inc -gen-disassembler)
tablegen(X86GenInstrNames.inc -gen-instr-enums) tablegen(X86GenInstrNames.inc -gen-instr-enums)

3
lib/Target/X86/Disassembler/X86Disassembler.cpp
View File

@ -26,7 +26,8 @@
#include "llvm/Support/MemoryObject.h" #include "llvm/Support/MemoryObject.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
#include "X86GenRegisterNames.inc" #define GET_REGINFO_ENUM
#include "X86GenRegisterInfo.inc"
#include "X86GenEDInfo.inc" #include "X86GenEDInfo.inc"
using namespace llvm; using namespace llvm;

5
lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
View File

@ -27,12 +27,11 @@
using namespace llvm; using namespace llvm;
// Include the auto-generated portion of the assembly writer. // Include the auto-generated portion of the assembly writer.
#define GET_REGINFO_ENUM
#include "X86GenRegisterInfo.inc"
#define GET_INSTRUCTION_NAME #define GET_INSTRUCTION_NAME
#define PRINT_ALIAS_INSTR #define PRINT_ALIAS_INSTR
#include "X86GenRegisterNames.inc"
#include "X86GenAsmWriter.inc" #include "X86GenAsmWriter.inc"
#undef PRINT_ALIAS_INSTR
#undef GET_INSTRUCTION_NAME
X86ATTInstPrinter::X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI) X86ATTInstPrinter::X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI)
: MCInstPrinter(MAI) { : MCInstPrinter(MAI) {

4
lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp
View File

@ -14,7 +14,9 @@
#include "X86TargetDesc.h" #include "X86TargetDesc.h"
#include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Target/TargetRegistry.h" #include "llvm/Target/TargetRegistry.h"
#include "X86GenRegisterDesc.inc"
#define GET_REGINFO_MC_DESC
#include "X86GenRegisterInfo.inc"
using namespace llvm; using namespace llvm;
MCRegisterInfo *createX86MCRegisterInfo() { MCRegisterInfo *createX86MCRegisterInfo() {

3
lib/Target/X86/MCTargetDesc/X86TargetDesc.h
View File

@ -23,6 +23,7 @@ extern Target TheX86_32Target, TheX86_64Target;
// Defines symbolic names for X86 registers. This defines a mapping from // Defines symbolic names for X86 registers. This defines a mapping from
// register name to register number. // register name to register number.
// //
#include "X86GenRegisterNames.inc" #define GET_REGINFO_ENUM
#include "X86GenRegisterInfo.inc"
#endif #endif

3
lib/Target/X86/Makefile
View File

@ -12,8 +12,7 @@ LIBRARYNAME = LLVMX86CodeGen
TARGET = X86 TARGET = X86
# Make sure that tblgen is run, first thing. # Make sure that tblgen is run, first thing.
BUILT_SOURCES = X86GenRegisterNames.inc X86GenRegisterDesc.inc \ BUILT_SOURCES = X86GenRegisterInfo.inc \
X86GenRegisterInfo.h.inc X86GenRegisterInfo.inc \
X86GenInstrNames.inc X86GenInstrInfo.inc \ X86GenInstrNames.inc X86GenInstrInfo.inc \
X86GenAsmWriter.inc X86GenAsmMatcher.inc \ X86GenAsmWriter.inc X86GenAsmMatcher.inc \
X86GenAsmWriter1.inc X86GenDAGISel.inc \ X86GenAsmWriter1.inc X86GenDAGISel.inc \

5
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -39,8 +39,11 @@
#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/STLExtras.h"
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/CommandLine.h" #include "llvm/Support/CommandLine.h"
#include "X86GenRegisterDesc.inc"
#define GET_REGINFO_MC_DESC
#define GET_REGINFO_TARGET_DESC
#include "X86GenRegisterInfo.inc" #include "X86GenRegisterInfo.inc"
using namespace llvm; using namespace llvm;
cl::opt<bool> cl::opt<bool>

4
lib/Target/X86/X86RegisterInfo.h
View File

@ -15,7 +15,9 @@
#define X86REGISTERINFO_H #define X86REGISTERINFO_H
#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetRegisterInfo.h"
#include "X86GenRegisterInfo.h.inc"
#define GET_REGINFO_HEADER
#include "X86GenRegisterInfo.inc"
namespace llvm { namespace llvm {
class Type; class Type;

3
lib/Target/XCore/CMakeLists.txt
View File

@ -1,8 +1,5 @@
set(LLVM_TARGET_DEFINITIONS XCore.td) set(LLVM_TARGET_DEFINITIONS XCore.td)
tablegen(XCoreGenRegisterNames.inc -gen-register-enums)
tablegen(XCoreGenRegisterDesc.inc -gen-register-desc)
tablegen(XCoreGenRegisterInfo.h.inc -gen-register-info-header)
tablegen(XCoreGenRegisterInfo.inc -gen-register-info) tablegen(XCoreGenRegisterInfo.inc -gen-register-info)
tablegen(XCoreGenInstrNames.inc -gen-instr-enums) tablegen(XCoreGenInstrNames.inc -gen-instr-enums)
tablegen(XCoreGenInstrInfo.inc -gen-instr-desc) tablegen(XCoreGenInstrInfo.inc -gen-instr-desc)

4
lib/Target/XCore/Makefile
View File

@ -12,9 +12,7 @@ LIBRARYNAME = LLVMXCoreCodeGen
TARGET = XCore TARGET = XCore
# Make sure that tblgen is run, first thing. # Make sure that tblgen is run, first thing.
BUILT_SOURCES = XCoreGenRegisterInfo.h.inc XCoreGenRegisterNames.inc \ BUILT_SOURCES = XCoreGenRegisterInfo.inc XCoreGenInstrNames.inc \
XCoreGenRegisterInfo.inc XCoreGenRegisterDesc.inc \
XCoreGenInstrNames.inc \
XCoreGenInstrInfo.inc XCoreGenAsmWriter.inc \ XCoreGenInstrInfo.inc XCoreGenAsmWriter.inc \
XCoreGenDAGISel.inc XCoreGenCallingConv.inc \ XCoreGenDAGISel.inc XCoreGenCallingConv.inc \
XCoreGenSubtarget.inc XCoreGenSubtarget.inc

3
lib/Target/XCore/XCore.h
View File

@ -32,7 +32,8 @@ namespace llvm {
// Defines symbolic names for XCore registers. This defines a mapping from // Defines symbolic names for XCore registers. This defines a mapping from
// register name to register number. // register name to register number.
// //
#include "XCoreGenRegisterNames.inc" #define GET_REGINFO_ENUM
#include "XCoreGenRegisterInfo.inc"
// Defines symbolic names for the XCore instructions. // Defines symbolic names for the XCore instructions.
// //

5
lib/Target/XCore/XCoreRegisterInfo.cpp
View File

@ -32,8 +32,11 @@
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
#include "XCoreGenRegisterDesc.inc"
#define GET_REGINFO_MC_DESC
#define GET_REGINFO_TARGET_DESC
#include "XCoreGenRegisterInfo.inc" #include "XCoreGenRegisterInfo.inc"
using namespace llvm; using namespace llvm;
XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii) XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)

4
lib/Target/XCore/XCoreRegisterInfo.h
View File

@ -15,7 +15,9 @@
#define XCOREREGISTERINFO_H #define XCOREREGISTERINFO_H
#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetRegisterInfo.h"
#include "XCoreGenRegisterInfo.h.inc"
#define GET_REGINFO_HEADER
#include "XCoreGenRegisterInfo.inc"
namespace llvm { namespace llvm {

261
utils/TableGen/RegisterInfoEmitter.cpp
View File

@ -25,14 +25,18 @@
using namespace llvm; using namespace llvm;
// runEnums - Print out enum values for all of the registers. // runEnums - Print out enum values for all of the registers.
void RegisterInfoEmitter::runEnums(raw_ostream &OS) { void
CodeGenTarget Target(Records); RegisterInfoEmitter::runEnums(raw_ostream &OS,
CodeGenRegBank &Bank = Target.getRegBank(); CodeGenTarget &Target, CodeGenRegBank &Bank) {
const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters(); const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace"); std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
EmitSourceFileHeader("Target Register Enum Values", OS); EmitSourceFileHeader("Target Register Enum Values", OS);
OS << "\n#ifdef GET_REGINFO_ENUM\n";
OS << "#undef GET_REGINFO_ENUM\n";
OS << "namespace llvm {\n\n"; OS << "namespace llvm {\n\n";
if (!Namespace.empty()) if (!Namespace.empty())
@ -63,12 +67,33 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS) {
if (!Namespace.empty()) if (!Namespace.empty())
OS << "}\n"; OS << "}\n";
} }
const std::vector<CodeGenRegisterClass> &RegisterClasses =
Target.getRegisterClasses();
if (!RegisterClasses.empty()) {
OS << "\n// Register classes\n";
OS << "namespace " << RegisterClasses[0].Namespace << " {\n";
OS << "enum {\n";
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
if (i) OS << ",\n";
OS << " " << RegisterClasses[i].getName() << "RegClassID";
OS << " = " << i;
}
OS << "\n };\n";
OS << "}\n";
}
OS << "} // End llvm namespace \n"; OS << "} // End llvm namespace \n";
OS << "#endif // GET_REGINFO_ENUM\n\n";
} }
void RegisterInfoEmitter::runHeader(raw_ostream &OS) { void RegisterInfoEmitter::runHeader(raw_ostream &OS, CodeGenTarget &Target) {
EmitSourceFileHeader("Register Information Header Fragment", OS); EmitSourceFileHeader("Register Information Header Fragment", OS);
CodeGenTarget Target(Records);
OS << "\n#ifdef GET_REGINFO_HEADER\n";
OS << "#undef GET_REGINFO_HEADER\n";
const std::string &TargetName = Target.getName(); const std::string &TargetName = Target.getName();
std::string ClassName = TargetName + "GenRegisterInfo"; std::string ClassName = TargetName + "GenRegisterInfo";
@ -100,14 +125,6 @@ void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
OS << "namespace " << RegisterClasses[0].Namespace OS << "namespace " << RegisterClasses[0].Namespace
<< " { // Register classes\n"; << " { // Register classes\n";
OS << " enum {\n";
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
if (i) OS << ",\n";
OS << " " << RegisterClasses[i].getName() << "RegClassID";
OS << " = " << i;
}
OS << "\n };\n\n";
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
const CodeGenRegisterClass &RC = RegisterClasses[i]; const CodeGenRegisterClass &RC = RegisterClasses[i];
const std::string &Name = RC.getName(); const std::string &Name = RC.getName();
@ -129,17 +146,125 @@ void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
OS << "} // end of namespace " << TargetName << "\n\n"; OS << "} // end of namespace " << TargetName << "\n\n";
} }
OS << "} // End llvm namespace \n"; OS << "} // End llvm namespace \n";
OS << "#endif // GET_REGINFO_HEADER\n\n";
} }
// //
// RegisterInfoEmitter::run - Main register file description emitter. // runMCDesc - Print out MC register descriptions.
// //
void RegisterInfoEmitter::run(raw_ostream &OS) { void
CodeGenTarget Target(Records); RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
CodeGenRegBank &RegBank = Target.getRegBank(); CodeGenRegBank &RegBank) {
RegBank.computeDerivedInfo(); EmitSourceFileHeader("MC Register Information", OS);
EmitSourceFileHeader("Register Information Source Fragment", OS); OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
OS << "#undef GET_REGINFO_MC_DESC\n";
std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
RegBank.computeOverlaps(Overlaps);
OS << "namespace llvm {\n\n";
const std::string &TargetName = Target.getName();
std::string ClassName = TargetName + "GenMCRegisterInfo";
OS << "struct " << ClassName << " : public MCRegisterInfo {\n"
<< " explicit " << ClassName << "(const MCRegisterDesc *D);\n";
OS << "};\n";
OS << "\nnamespace {\n";
const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
// Emit an overlap list for all registers.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister *Reg = Regs[i];
const CodeGenRegister::Set &O = Overlaps[Reg];
// Move Reg to the front so TRI::getAliasSet can share the list.
OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { "
<< getQualifiedName(Reg->TheDef) << ", ";
for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
I != E; ++I)
if (*I != Reg)
OS << getQualifiedName((*I)->TheDef) << ", ";
OS << "0 };\n";
}
// Emit the empty sub-registers list
OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
// Loop over all of the registers which have sub-registers, emitting the
// sub-registers list to memory.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister &Reg = *Regs[i];
if (Reg.getSubRegs().empty())
continue;
// getSubRegs() orders by SubRegIndex. We want a topological order.
SetVector<CodeGenRegister*> SR;
Reg.addSubRegsPreOrder(SR);
OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
for (unsigned j = 0, je = SR.size(); j != je; ++j)
OS << getQualifiedName(SR[j]->TheDef) << ", ";
OS << "0 };\n";
}
// Emit the empty super-registers list
OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
// Loop over all of the registers which have super-registers, emitting the
// super-registers list to memory.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister &Reg = *Regs[i];
const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
if (SR.empty())
continue;
OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { ";
for (unsigned j = 0, je = SR.size(); j != je; ++j)
OS << getQualifiedName(SR[j]->TheDef) << ", ";
OS << "0 };\n";
}
OS << "\n const MCRegisterDesc " << TargetName
<< "RegDesc[] = { // Descriptors\n";
OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
// Now that register alias and sub-registers sets have been emitted, emit the
// register descriptors now.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister &Reg = *Regs[i];
OS << " { \"";
OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
if (!Reg.getSubRegs().empty())
OS << Reg.getName() << "_SubRegsSet,\t";
else
OS << "Empty_SubRegsSet,\t";
if (!Reg.getSuperRegs().empty())
OS << Reg.getName() << "_SuperRegsSet";
else
OS << "Empty_SuperRegsSet";
OS << " },\n";
}
OS << " };\n"; // End of register descriptors...
OS << "}\n\n"; // End of anonymous namespace...
// MCRegisterInfo initialization routine.
OS << "static inline void Init" << TargetName
<< "MCRegisterInfo(MCRegisterInfo *RI) {\n";
OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
<< Regs.size()+1 << ");\n}\n\n";
OS << "} // End llvm namespace \n";
OS << "#endif // GET_REGINFO_MC_DESC\n\n";
}
//
// runTargetDesc - Output the target register and register file descriptions.
//
void
RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
CodeGenRegBank &RegBank){
EmitSourceFileHeader("Target Register and Register Classes Information", OS);
OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
OS << "#undef GET_REGINFO_TARGET_DESC\n";
OS << "namespace llvm {\n\n"; OS << "namespace llvm {\n\n";
@ -614,102 +739,16 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
OS << " };\n}\n\n"; OS << " };\n}\n\n";
OS << "} // End llvm namespace \n"; OS << "} // End llvm namespace \n";
OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
} }
void RegisterInfoEmitter::runDesc(raw_ostream &OS) { void RegisterInfoEmitter::run(raw_ostream &OS) {
CodeGenTarget Target(Records); CodeGenTarget Target(Records);
CodeGenRegBank &RegBank = Target.getRegBank(); CodeGenRegBank &RegBank = Target.getRegBank();
RegBank.computeDerivedInfo(); RegBank.computeDerivedInfo();
std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
RegBank.computeOverlaps(Overlaps);
OS << "namespace llvm {\n\n"; runEnums(OS, Target, RegBank);
runHeader(OS, Target);
const std::string &TargetName = Target.getName(); runMCDesc(OS, Target, RegBank);
std::string ClassName = TargetName + "GenMCRegisterInfo"; runTargetDesc(OS, Target, RegBank);
OS << "struct " << ClassName << " : public MCRegisterInfo {\n"
<< " explicit " << ClassName << "(const MCRegisterDesc *D);\n";
OS << "};\n";
OS << "\nnamespace {\n";
const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
// Emit an overlap list for all registers.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister *Reg = Regs[i];
const CodeGenRegister::Set &O = Overlaps[Reg];
// Move Reg to the front so TRI::getAliasSet can share the list.
OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { "
<< getQualifiedName(Reg->TheDef) << ", ";
for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
I != E; ++I)
if (*I != Reg)
OS << getQualifiedName((*I)->TheDef) << ", ";
OS << "0 };\n";
}
// Emit the empty sub-registers list
OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
// Loop over all of the registers which have sub-registers, emitting the
// sub-registers list to memory.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister &Reg = *Regs[i];
if (Reg.getSubRegs().empty())
continue;
// getSubRegs() orders by SubRegIndex. We want a topological order.
SetVector<CodeGenRegister*> SR;
Reg.addSubRegsPreOrder(SR);
OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
for (unsigned j = 0, je = SR.size(); j != je; ++j)
OS << getQualifiedName(SR[j]->TheDef) << ", ";
OS << "0 };\n";
}
// Emit the empty super-registers list
OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
// Loop over all of the registers which have super-registers, emitting the
// super-registers list to memory.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister &Reg = *Regs[i];
const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
if (SR.empty())
continue;
OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { ";
for (unsigned j = 0, je = SR.size(); j != je; ++j)
OS << getQualifiedName(SR[j]->TheDef) << ", ";
OS << "0 };\n";
}
OS << "\n const MCRegisterDesc " << TargetName
<< "RegDesc[] = { // Descriptors\n";
OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
// Now that register alias and sub-registers sets have been emitted, emit the
// register descriptors now.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister &Reg = *Regs[i];
OS << " { \"";
OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
if (!Reg.getSubRegs().empty())
OS << Reg.getName() << "_SubRegsSet,\t";
else
OS << "Empty_SubRegsSet,\t";
if (!Reg.getSuperRegs().empty())
OS << Reg.getName() << "_SuperRegsSet";
else
OS << "Empty_SuperRegsSet";
OS << " },\n";
}
OS << " };\n"; // End of register descriptors...
OS << "}\n\n"; // End of anonymous namespace...
// MCRegisterInfo initialization routine.
OS << "static inline void Init" << TargetName
<< "MCRegisterInfo(MCRegisterInfo *RI) {\n";
OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
<< Regs.size()+1 << ");\n}\n\n";
OS << "} // End llvm namespace \n";
} }

20
utils/TableGen/RegisterInfoEmitter.h
View File

@ -20,22 +20,28 @@
namespace llvm { namespace llvm {
class CodeGenRegBank;
class CodeGenTarget;
class RegisterInfoEmitter : public TableGenBackend { class RegisterInfoEmitter : public TableGenBackend {
RecordKeeper &Records; RecordKeeper &Records;
public: public:
RegisterInfoEmitter(RecordKeeper &R) : Records(R) {} RegisterInfoEmitter(RecordKeeper &R) : Records(R) {}
// run - Output the register file description, returning true on failure. // runEnums - Print out enum values for all of the registers.
void run(raw_ostream &o); void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
// runHeader - Emit a header fragment for the register info emitter. // runHeader - Emit a header fragment for the register info emitter.
void runHeader(raw_ostream &o); void runHeader(raw_ostream &o, CodeGenTarget &Target);
// runEnums - Print out enum values for all of the registers. // runMCDesc - Print out MC register descriptions.
void runEnums(raw_ostream &o); void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
// runDesc - Print out register descriptions. // runTargetDesc - Output the target register and register file descriptions.
void runDesc(raw_ostream &o); void runTargetDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
// run - Output the register file description.
void run(raw_ostream &o);
}; };
} // End llvm namespace } // End llvm namespace

19
utils/TableGen/TableGen.cpp
View File

@ -54,7 +54,7 @@ using namespace llvm;
enum ActionType { enum ActionType {
PrintRecords, PrintRecords,
GenEmitter, GenEmitter,
GenRegisterEnums, GenRegisterDesc, GenRegisterInfo, GenRegisterInfoHeader, GenRegisterInfo,
GenInstrEnums, GenInstrs, GenAsmWriter, GenAsmMatcher, GenInstrEnums, GenInstrs, GenAsmWriter, GenAsmMatcher,
GenARMDecoder, GenARMDecoder,
GenDisassembler, GenDisassembler,
@ -93,14 +93,8 @@ namespace {
"Print all records to stdout (default)"), "Print all records to stdout (default)"),
clEnumValN(GenEmitter, "gen-emitter", clEnumValN(GenEmitter, "gen-emitter",
"Generate machine code emitter"), "Generate machine code emitter"),
clEnumValN(GenRegisterEnums, "gen-register-enums",
"Generate enum values for registers"),
clEnumValN(GenRegisterDesc, "gen-register-desc",
"Generate register descriptions"),
clEnumValN(GenRegisterInfo, "gen-register-info", clEnumValN(GenRegisterInfo, "gen-register-info",
"Generate registers & reg-classes info"), "Generate registers and register classes info"),
clEnumValN(GenRegisterInfoHeader, "gen-register-info-header",
"Generate registers & reg-classes info header"),
clEnumValN(GenInstrEnums, "gen-instr-enums", clEnumValN(GenInstrEnums, "gen-instr-enums",
"Generate enum values for instructions"), "Generate enum values for instructions"),
clEnumValN(GenInstrs, "gen-instr-desc", clEnumValN(GenInstrs, "gen-instr-desc",
@ -263,18 +257,9 @@ int main(int argc, char **argv) {
case GenEmitter: case GenEmitter:
CodeEmitterGen(Records).run(Out.os()); CodeEmitterGen(Records).run(Out.os());
break; break;
case GenRegisterEnums:
RegisterInfoEmitter(Records).runEnums(Out.os());
break;
case GenRegisterDesc:
RegisterInfoEmitter(Records).runDesc(Out.os());
break;
case GenRegisterInfo: case GenRegisterInfo:
RegisterInfoEmitter(Records).run(Out.os()); RegisterInfoEmitter(Records).run(Out.os());
break; break;
case GenRegisterInfoHeader:
RegisterInfoEmitter(Records).runHeader(Out.os());
break;
case GenInstrEnums: case GenInstrEnums:
InstrEnumEmitter(Records).run(Out.os()); InstrEnumEmitter(Records).run(Out.os());
break; break;