6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-03-26 07:34:14 +00:00
Code Issues Projects Releases Wiki Activity

add patterns for ppc32 preinc stores. ppc64 next.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31775 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-11-16 00:41:37 +00:00
parent ef20fefa65
commit 74531e49ef
2 changed files with 22 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -108,6 +108,14 @@ namespace {
SDOperand &Base) { SDOperand &Base) {
return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG); return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG);
} }
/// SelectAddrImmOffs - Return true if the operand is valid for a preinc
/// immediate field. Because preinc imms have already been validated, just
/// accept it.
bool SelectAddrImmOffs(SDOperand Op, SDOperand N, SDOperand &Out) const {
Out = N;
return true;
}
/// SelectAddrIdx - Given the specified addressed, check to see if it can be /// SelectAddrIdx - Given the specified addressed, check to see if it can be
/// represented as an indexed [r+r] operation. Returns false if it can /// represented as an indexed [r+r] operation. Returns false if it can

21
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -273,6 +273,8 @@ def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std" def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
/// This is just the offset part of iaddr, used for preinc.
def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// PowerPC Instruction Predicate Definitions. // PowerPC Instruction Predicate Definitions.
@ -531,29 +533,34 @@ let isStore = 1, PPC970_Unit = 2 in {
def STBU : DForm_1<39, (ops ptr_rc:$ea_res, GPRC:$rS, def STBU : DForm_1<39, (ops ptr_rc:$ea_res, GPRC:$rS,
symbolLo:$ptroff, ptr_rc:$ptrreg), symbolLo:$ptroff, ptr_rc:$ptrreg),
"stbu $rS, $ptroff($ptrreg)", LdStGeneral, "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
[/*(set ptr_rc:$ea_res, [(set ptr_rc:$ea_res,
(pre_truncsti8 GPRC:$rS, iaddr:$addr))*/]>, (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
iaddroff:$ptroff))]>,
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
def STHU : DForm_1<37, (ops ptr_rc:$ea_res, GPRC:$rS, def STHU : DForm_1<37, (ops ptr_rc:$ea_res, GPRC:$rS,
symbolLo:$ptroff, ptr_rc:$ptrreg), symbolLo:$ptroff, ptr_rc:$ptrreg),
"sthu $rS, $ptroff($ptrreg)", LdStGeneral, "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
[/*(set ptr_rc:$ea_res, [(set ptr_rc:$ea_res,
(pre_truncsti16 GPRC:$rS, iaddr:$addr))*/]>, (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
iaddroff:$ptroff))]>,
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
def STWU : DForm_1<37, (ops ptr_rc:$ea_res, GPRC:$rS, def STWU : DForm_1<37, (ops ptr_rc:$ea_res, GPRC:$rS,
symbolLo:$ptroff, ptr_rc:$ptrreg), symbolLo:$ptroff, ptr_rc:$ptrreg),
"stwu $rS, $ptroff($ptrreg)", LdStGeneral, "stwu $rS, $ptroff($ptrreg)", LdStGeneral,
[/*(set ptr_rc:$ea_res, (pre_store GPRC:$rS, iaddr:$addr))*/]>, [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg,
iaddroff:$ptroff))]>,
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
def STFSU : DForm_1<37, (ops ptr_rc:$ea_res, F4RC:$rS, def STFSU : DForm_1<37, (ops ptr_rc:$ea_res, F4RC:$rS,
symbolLo:$ptroff, ptr_rc:$ptrreg), symbolLo:$ptroff, ptr_rc:$ptrreg),
"stfsu $rS, $ptroff($ptrreg)", LdStGeneral, "stfsu $rS, $ptroff($ptrreg)", LdStGeneral,
[/*(set ptr_rc:$ea_res, (pre_store F4RC:$rS, iaddr:$addr))*/]>, [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg,
iaddroff:$ptroff))]>,
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
def STFDU : DForm_1<37, (ops ptr_rc:$ea_res, F8RC:$rS, def STFDU : DForm_1<37, (ops ptr_rc:$ea_res, F8RC:$rS,
symbolLo:$ptroff, ptr_rc:$ptrreg), symbolLo:$ptroff, ptr_rc:$ptrreg),
"stfdu $rS, $ptroff($ptrreg)", LdStGeneral, "stfdu $rS, $ptroff($ptrreg)", LdStGeneral,
[/*(set ptr_rc:$ea_res, (pre_store F8RC:$rS, iaddr:$addr))*/]>, [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg,
iaddroff:$ptroff))]>,
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
} }