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Merging r201507:

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r201507 | craig.topper | 2014-02-17 05:03:43 -0500 (Mon, 17 Feb 2014) | 2 lines

Fix diassembler handling of rex.b when mod=00/01/10 and bbb=101. Mod=00 should ignore the base register entirely. Mod=01/10 should treat this as R13 plus displacment. Fixes PR18860.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@206056 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard committed 2014-04-11 19:35:46 +00:00
1 parent 3830243b55
commit 7491fd3143
2 files changed
+27 -4
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lib/Target/X86/Disassembler/X86DisassemblerDecoder.c
+3 -4
View File
@@ -1065,6 +1065,7 @@ static int readSIB(struct InternalInstruction* insn) {
switch (base) {
case 0x5:
case 0xd:
switch (modFromModRM(insn->modRM)) {
case 0x0:
insn->eaDisplacement = EA_DISP_32;
@@ -1072,13 +1073,11 @@ static int readSIB(struct InternalInstruction* insn) {
break;
case 0x1:
insn->eaDisplacement = EA_DISP_8;
insn->sibBase = (insn->addressSize == 4 ?
SIB_BASE_EBP : SIB_BASE_RBP);
insn->sibBase = (SIBBase)(sibBaseBase + base);
break;
case 0x2:
insn->eaDisplacement = EA_DISP_32;
insn->sibBase = (insn->addressSize == 4 ?
SIB_BASE_EBP : SIB_BASE_RBP);
insn->sibBase = (SIBBase)(sibBaseBase + base);
break;
case 0x3:
debug("Cannot have Mod = 0b11 and a SIB byte");
test/MC/Disassembler/X86/x86-64.txt
+24
View File
@@ -241,3 +241,27 @@
# CHECK: pextrw $3, %xmm3, (%rax)
0x66 0x0f 0x3a 0x15 0x18 0x03
# CHECK: $0, 305419896(,%r8)
0x43 0x80 0x04 0x05 0x78 0x56 0x34 0x12 0x00
# CHECK: $0, 305419896(%r13,%r8)
0x43 0x80 0x84 0x05 0x78 0x56 0x34 0x12 0x00
# CHECK: $0, 305419896(,%r8)
0x42 0x80 0x04 0x05 0x78 0x56 0x34 0x12 0x00
# CHECK: $0, 305419896(%rbp,%r8)
0x42 0x80 0x84 0x05 0x78 0x56 0x34 0x12 0x00
# CHECK: $0, 305419896(,%r12)
0x42 0x80 0x04 0x25 0x78 0x56 0x34 0x12 0x00
# CHECK: $0, 305419896(%rbp,%r12)
0x42 0x80 0x84 0x25 0x78 0x56 0x34 0x12 0x00
# CHECK: $0, 305419896
0x80 0x04 0x25 0x78 0x56 0x34 0x12 0x00
# CHECK: $0, 305419896(%rbp)
0x80 0x84 0x25 0x78 0x56 0x34 0x12 0x00