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R600/SI: Make sure M0 is loaded for V_INTERP_MOV_F32
NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175733 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1311,7 +1311,8 @@ def : Pat <
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def : Pat <
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(int_SI_fs_interp_constant imm:$attr_chan, imm:$attr, SReg_32:$params),
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(V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, SReg_32:$params)
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(V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr,
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(S_MOV_B32 SReg_32:$params))
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>;
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def : Pat <
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23
test/CodeGen/R600/llvm.SI.fs.interp.constant.ll
Normal file
23
test/CodeGen/R600/llvm.SI.fs.interp.constant.ll
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@ -0,0 +1,23 @@
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;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
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;CHECK: S_MOV_B32
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;CHECK-NEXT: V_INTERP_MOV_F32
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define void @main() {
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main_body:
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call void @llvm.AMDGPU.shader.type(i32 0)
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%0 = load i32 addrspace(8)* inttoptr (i32 6 to i32 addrspace(8)*)
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%1 = call float @llvm.SI.fs.interp.constant(i32 0, i32 0, i32 %0)
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%2 = call i32 @llvm.SI.packf16(float %1, float %1)
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%3 = bitcast i32 %2 to float
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float %3)
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ret void
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}
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declare void @llvm.AMDGPU.shader.type(i32)
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declare float @llvm.SI.fs.interp.constant(i32, i32, i32) readonly
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declare i32 @llvm.SI.packf16(float, float) readnone
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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