R600/SI: Make sure M0 is loaded for V_INTERP_MOV_F32

NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175733 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Michel Danzer 2013-02-21 08:57:10 +00:00
parent 197a60a666
commit 74bf7a8467
2 changed files with 25 additions and 1 deletions

View File

@ -1311,7 +1311,8 @@ def : Pat <
def : Pat <
(int_SI_fs_interp_constant imm:$attr_chan, imm:$attr, SReg_32:$params),
(V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, SReg_32:$params)
(V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr,
(S_MOV_B32 SReg_32:$params))
>;
def : Pat <

View File

@ -0,0 +1,23 @@
;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
;CHECK: S_MOV_B32
;CHECK-NEXT: V_INTERP_MOV_F32
define void @main() {
main_body:
call void @llvm.AMDGPU.shader.type(i32 0)
%0 = load i32 addrspace(8)* inttoptr (i32 6 to i32 addrspace(8)*)
%1 = call float @llvm.SI.fs.interp.constant(i32 0, i32 0, i32 %0)
%2 = call i32 @llvm.SI.packf16(float %1, float %1)
%3 = bitcast i32 %2 to float
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float %3)
ret void
}
declare void @llvm.AMDGPU.shader.type(i32)
declare float @llvm.SI.fs.interp.constant(i32, i32, i32) readonly
declare i32 @llvm.SI.packf16(float, float) readnone
declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)