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R600: Use range for and fix missing consts.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212897 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-07-13 03:06:43 +00:00
parent bb098a4d87
commit 74c9fe26e6
2 changed files with 20 additions and 29 deletions
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41
lib/Target/R600/AMDGPUAsmPrinter.cpp
View File

@ -47,7 +47,7 @@ using namespace llvm;
// precision, and leaves single precision to flush all and does not report // precision, and leaves single precision to flush all and does not report
// CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
// CL_FP_DENORM for both. // CL_FP_DENORM for both.
static uint32_t getFPMode(MachineFunction &) { static uint32_t getFPMode(const MachineFunction &) {
return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) | return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) | FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
FP_DENORM_MODE_SP(FP_DENORM_FLUSH_NONE) | FP_DENORM_MODE_SP(FP_DENORM_FLUSH_NONE) |
@ -144,25 +144,21 @@ bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
return false; return false;
} }
void AMDGPUAsmPrinter::EmitProgramInfoR600(MachineFunction &MF) { void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
unsigned MaxGPR = 0; unsigned MaxGPR = 0;
bool killPixel = false; bool killPixel = false;
const R600RegisterInfo * RI = const R600RegisterInfo *RI
static_cast<const R600RegisterInfo*>(TM.getRegisterInfo()); = static_cast<const R600RegisterInfo*>(TM.getRegisterInfo());
R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>(); const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>(); const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end(); for (const MachineBasicBlock &MBB : MF) {
BB != BB_E; ++BB) { for (const MachineInstr &MI : MBB) {
MachineBasicBlock &MBB = *BB;
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
I != E; ++I) {
MachineInstr &MI = *I;
if (MI.getOpcode() == AMDGPU::KILLGT) if (MI.getOpcode() == AMDGPU::KILLGT)
killPixel = true; killPixel = true;
unsigned numOperands = MI.getNumOperands(); unsigned numOperands = MI.getNumOperands();
for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) { for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
MachineOperand & MO = MI.getOperand(op_idx); const MachineOperand &MO = MI.getOperand(op_idx);
if (!MO.isReg()) if (!MO.isReg())
continue; continue;
unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff; unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
@ -209,27 +205,22 @@ void AMDGPUAsmPrinter::EmitProgramInfoR600(MachineFunction &MF) {
} }
void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo, void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
MachineFunction &MF) const { const MachineFunction &MF) const {
uint64_t CodeSize = 0; uint64_t CodeSize = 0;
unsigned MaxSGPR = 0; unsigned MaxSGPR = 0;
unsigned MaxVGPR = 0; unsigned MaxVGPR = 0;
bool VCCUsed = false; bool VCCUsed = false;
const SIRegisterInfo * RI = const SIRegisterInfo *RI
static_cast<const SIRegisterInfo*>(TM.getRegisterInfo()); = static_cast<const SIRegisterInfo*>(TM.getRegisterInfo());
for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
BB != BB_E; ++BB) {
MachineBasicBlock &MBB = *BB;
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
I != E; ++I) {
MachineInstr &MI = *I;
for (const MachineBasicBlock &MBB : MF) {
for (const MachineInstr &MI : MBB) {
// TODO: CodeSize should account for multiple functions. // TODO: CodeSize should account for multiple functions.
CodeSize += MI.getDesc().Size; CodeSize += MI.getDesc().Size;
unsigned numOperands = MI.getNumOperands(); unsigned numOperands = MI.getNumOperands();
for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) { for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
MachineOperand &MO = MI.getOperand(op_idx); const MachineOperand &MO = MI.getOperand(op_idx);
unsigned width = 0; unsigned width = 0;
bool isSGPR = false; bool isSGPR = false;
@ -317,10 +308,10 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
ProgInfo.CodeLen = CodeSize; ProgInfo.CodeLen = CodeSize;
} }
void AMDGPUAsmPrinter::EmitProgramInfoSI(MachineFunction &MF, void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
const SIProgramInfo &KernelInfo) { const SIProgramInfo &KernelInfo) {
const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>(); const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
unsigned RsrcReg; unsigned RsrcReg;
switch (MFI->getShaderType()) { switch (MFI->getShaderType()) {

8
lib/Target/R600/AMDGPUAsmPrinter.h
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@ -49,15 +49,15 @@ private:
uint64_t CodeLen; uint64_t CodeLen;
}; };
void getSIProgramInfo(SIProgramInfo &Out, MachineFunction &MF) const; void getSIProgramInfo(SIProgramInfo &Out, const MachineFunction &MF) const;
void findNumUsedRegistersSI(MachineFunction &MF, void findNumUsedRegistersSI(const MachineFunction &MF,
unsigned &NumSGPR, unsigned &NumSGPR,
unsigned &NumVGPR) const; unsigned &NumVGPR) const;
/// \brief Emit register usage information so that the GPU driver /// \brief Emit register usage information so that the GPU driver
/// can correctly setup the GPU state. /// can correctly setup the GPU state.
void EmitProgramInfoR600(MachineFunction &MF); void EmitProgramInfoR600(const MachineFunction &MF);
void EmitProgramInfoSI(MachineFunction &MF, const SIProgramInfo &KernelInfo); void EmitProgramInfoSI(const MachineFunction &MF, const SIProgramInfo &KernelInfo);
public: public:
explicit AMDGPUAsmPrinter(TargetMachine &TM, MCStreamer &Streamer); explicit AMDGPUAsmPrinter(TargetMachine &TM, MCStreamer &Streamer);