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Strange as it may sound, we'll not use LDD/STD to store longs. For reasons of

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representational consistency, we want to address the halves of each 64-bit value
separately.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14356 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Brian Gaeke 2004-06-24 06:44:57 +00:00
parent 00e514ea6a
commit 7548a540f7
4 changed files with 16 additions and 8 deletions
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6
lib/Target/Sparc/InstSelectSimple.cpp
View File

@ -546,7 +546,8 @@ void V8ISel::visitLoadInst(LoadInst &I) {
BuildMI (BB, V8::LDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
return;
case cLong:
BuildMI (BB, V8::LDDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
BuildMI (BB, V8::LDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
BuildMI (BB, V8::LDmr, 1, DestReg+1).addReg (PtrReg).addSImm(4);
return;
default:
std::cerr << "Load instruction not handled: " << I;
@ -570,7 +571,8 @@ void V8ISel::visitStoreInst(StoreInst &I) {
BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
return;
case cLong:
BuildMI (BB, V8::STDrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (4).addReg (SrcReg+1);
return;
default:
std::cerr << "Store instruction not handled: " << I;

6
lib/Target/Sparc/SparcV8ISelSimple.cpp
View File

@ -546,7 +546,8 @@ void V8ISel::visitLoadInst(LoadInst &I) {
BuildMI (BB, V8::LDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
return;
case cLong:
BuildMI (BB, V8::LDDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
BuildMI (BB, V8::LDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
BuildMI (BB, V8::LDmr, 1, DestReg+1).addReg (PtrReg).addSImm(4);
return;
default:
std::cerr << "Load instruction not handled: " << I;
@ -570,7 +571,8 @@ void V8ISel::visitStoreInst(StoreInst &I) {
BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
return;
case cLong:
BuildMI (BB, V8::STDrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (4).addReg (SrcReg+1);
return;
default:
std::cerr << "Store instruction not handled: " << I;

6
lib/Target/SparcV8/InstSelectSimple.cpp
View File

@ -546,7 +546,8 @@ void V8ISel::visitLoadInst(LoadInst &I) {
BuildMI (BB, V8::LDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
return;
case cLong:
BuildMI (BB, V8::LDDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
BuildMI (BB, V8::LDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
BuildMI (BB, V8::LDmr, 1, DestReg+1).addReg (PtrReg).addSImm(4);
return;
default:
std::cerr << "Load instruction not handled: " << I;
@ -570,7 +571,8 @@ void V8ISel::visitStoreInst(StoreInst &I) {
BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
return;
case cLong:
BuildMI (BB, V8::STDrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (4).addReg (SrcReg+1);
return;
default:
std::cerr << "Store instruction not handled: " << I;

6
lib/Target/SparcV8/SparcV8ISelSimple.cpp
View File

@ -546,7 +546,8 @@ void V8ISel::visitLoadInst(LoadInst &I) {
BuildMI (BB, V8::LDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
return;
case cLong:
BuildMI (BB, V8::LDDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
BuildMI (BB, V8::LDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
BuildMI (BB, V8::LDmr, 1, DestReg+1).addReg (PtrReg).addSImm(4);
return;
default:
std::cerr << "Load instruction not handled: " << I;
@ -570,7 +571,8 @@ void V8ISel::visitStoreInst(StoreInst &I) {
BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
return;
case cLong:
BuildMI (BB, V8::STDrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
BuildMI (BB, V8::STrm, 3).addReg (PtrReg).addSImm (4).addReg (SrcReg+1);
return;
default:
std::cerr << "Store instruction not handled: " << I;