diff --git a/lib/Target/Sparc/SparcV8Reg.td b/lib/Target/Sparc/SparcV8Reg.td
index 3813d25261e..f58d06adf70 100644
--- a/lib/Target/Sparc/SparcV8Reg.td
+++ b/lib/Target/Sparc/SparcV8Reg.td
@@ -36,7 +36,7 @@ let Namespace = "SparcV8" in {
 // FIXME: the register order should be defined in terms of the preferred
 // allocation order...
 //
-def IntRegs : RegisterClass<i64, 8, [G0, G1, G2, G3, G4, G5, G6, G7,
+def IntRegs : RegisterClass<i32, 8, [G0, G1, G2, G3, G4, G5, G6, G7,
                                      O0, O1, O2, O3, O4, O5, O6, O7,
                                      L0, L1, L2, L3, L4, L5, L6, L7,
                                      I0, I1, I2, I3, I4, I5, I6, I7]>;
diff --git a/lib/Target/SparcV8/SparcV8Reg.td b/lib/Target/SparcV8/SparcV8Reg.td
index 3813d25261e..f58d06adf70 100644
--- a/lib/Target/SparcV8/SparcV8Reg.td
+++ b/lib/Target/SparcV8/SparcV8Reg.td
@@ -36,7 +36,7 @@ let Namespace = "SparcV8" in {
 // FIXME: the register order should be defined in terms of the preferred
 // allocation order...
 //
-def IntRegs : RegisterClass<i64, 8, [G0, G1, G2, G3, G4, G5, G6, G7,
+def IntRegs : RegisterClass<i32, 8, [G0, G1, G2, G3, G4, G5, G6, G7,
                                      O0, O1, O2, O3, O4, O5, O6, O7,
                                      L0, L1, L2, L3, L4, L5, L6, L7,
                                      I0, I1, I2, I3, I4, I5, I6, I7]>;