From 758df297412df99d737dfcaea09b5e7857f320e5 Mon Sep 17 00:00:00 2001 From: Johnny Chen Date: Tue, 22 Mar 2011 20:00:10 +0000 Subject: [PATCH] A8.6.399 VSTM: VFP Load/Store Multiple Instructions used to embed the IA/DB addressing mode within the MC instruction; that has been changed so that now, for example, VSTMDDB_UPD and VSTMDIA_UPD are two instructions. Update the ARMDisassemblerCore.cpp's DisassembleVFPLdStMulFrm() to reflect the change. Also add a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128103 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../ARM/Disassembler/ARMDisassemblerCore.cpp | 14 ++------------ test/MC/Disassembler/ARM/thumb-tests.txt | 3 +++ 2 files changed, 5 insertions(+), 12 deletions(-) diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index f8ba285f1ca..41b60ebc4cb 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -1799,9 +1799,8 @@ static bool DisassembleVFPLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn, } // VFP Load/Store Multiple Instructions. -// This is similar to the algorithm for LDM/STM in that operand 0 (the base) and -// operand 1 (the AM4 mode imm) is followed by two predicate operands. It is -// followed by a reglist of either DPR(s) or SPR(s). +// We have an optional write back reg, the base, and two predicate operands. +// It is then followed by a reglist of either DPR(s) or SPR(s). // // VLDMD[_UPD], VLDMS[_UPD], VSTMD[_UPD], VSTMS[_UPD] static bool DisassembleVFPLdStMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn, @@ -1826,15 +1825,6 @@ static bool DisassembleVFPLdStMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn, MI.addOperand(MCOperand::CreateReg(Base)); - // Next comes the AM4 Opcode. - ARM_AM::AMSubMode SubMode = getAMSubModeForBits(getPUBits(insn)); - // Must be either "ia" or "db" submode. - if (SubMode != ARM_AM::ia && SubMode != ARM_AM::db) { - DEBUG(errs() << "Illegal addressing mode 4 sub-mode!\n"); - return false; - } - MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM4ModeImm(SubMode))); - // Handling the two predicate operands before the reglist. int64_t CondVal = insn >> ARMII::CondShift; MI.addOperand(MCOperand::CreateImm(CondVal == 0xF ? 0xE : CondVal)); diff --git a/test/MC/Disassembler/ARM/thumb-tests.txt b/test/MC/Disassembler/ARM/thumb-tests.txt index 9036b56b2d7..b28c8829db3 100644 --- a/test/MC/Disassembler/ARM/thumb-tests.txt +++ b/test/MC/Disassembler/ARM/thumb-tests.txt @@ -130,3 +130,6 @@ # CHECK: blx #-4 0xff 0xf7 0xfe 0xef + +# CHECK: vpush {d8, d9, d10} +0x2d 0xed 0x06 0x8b