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[AArch64] Keep flags on condition vreg when instantiating a CB branch.
Reversing a CB* instruction used to drop the flags on the condition. On the included testcase, this lead to a read from an undefined vreg. Using addOperand keeps the flags, here <undef>. Differential Revision: http://reviews.llvm.org/D6159 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221507 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -261,8 +261,9 @@ void AArch64InstrInfo::instantiateCondBranch(
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BuildMI(&MBB, DL, get(AArch64::Bcc)).addImm(Cond[0].getImm()).addMBB(TBB);
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} else {
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// Folded compare-and-branch
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// Note that we use addOperand instead of addReg to keep the flags.
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const MachineInstrBuilder MIB =
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BuildMI(&MBB, DL, get(Cond[1].getImm())).addReg(Cond[2].getReg());
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BuildMI(&MBB, DL, get(Cond[1].getImm())).addOperand(Cond[2]);
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if (Cond.size() > 3)
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MIB.addImm(Cond[3].getImm());
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MIB.addMBB(TBB);
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26
test/CodeGen/AArch64/br-undef-cond.ll
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26
test/CodeGen/AArch64/br-undef-cond.ll
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@ -0,0 +1,26 @@
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; RUN: llc < %s -verify-machineinstrs
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; Make sure we don't end up with a CBNZ of an undef v-/phys-reg.
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "arm64-apple-ios"
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declare void @bar(i8*)
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define void @foo(i8* %m, i32 %off0) {
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.thread1653:
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br i1 undef, label %0, label %.thread1880
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%1 = icmp eq i32 undef, 0
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%.not = xor i1 %1, true
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%brmerge = or i1 %.not, undef
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br i1 %brmerge, label %.thread1880, label %.thread1705
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.thread1705:
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ret void
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.thread1880:
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%m1652.ph = phi i8* [ %m, %0 ], [ null, %.thread1653 ]
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call void @bar(i8* %m1652.ph)
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ret void
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}
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