6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-08-09 11:25:55 +00:00
Code Issues Projects Releases Wiki Activity

Fix Bug 9386 - ARM disassembler failed to disassemble conditional bx

Browse Source 
Modified the patch to .td file supplied by Jyun-Yan You.  Add a test case and
modified ARMDisassemblerCore.cpp a little bit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131859 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen
2011-05-22 17:51:04 +00:00
parent 4f81b54192
commit 75f4296c7c
3 changed files with 16 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
lib/Target/ARM/ARMInstrInfo.td
View File

@@ -1313,6 +1313,15 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
let Inst{3-0} = dst; let Inst{3-0} = dst;
} }
// For disassembly only.
def BX_pred : AXI<(outs), (ins GPR:$dst, pred:$p), BrMiscFrm, IIC_Br,
"bx$p\t$dst", [/* pattern left blank */]>,
Requires<[IsARM, HasV4T]> {
bits<4> dst;
let Inst{27-4} = 0b000100101111111111110001;
let Inst{3-0} = dst;
}
// ARMV4 only // ARMV4 only
// FIXME: We would really like to define this as a vanilla ARMPat like: // FIXME: We would really like to define this as a vanilla ARMPat like:
// ARMPat<(brind GPR:$dst), (MOVr PC, GPR:$dst)> // ARMPat<(brind GPR:$dst), (MOVr PC, GPR:$dst)>

7
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@@ -895,8 +895,9 @@ static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
} }
// Misc. Branch Instructions. // Misc. Branch Instructions.
// BLX, BLXi, BX // BX_RET, MOVPCLR
// BX, BX_RET // BLX, BLX_pred, BX, BX_pred
// BLXi
static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn, static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded, BO B) { unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
@@ -913,7 +914,7 @@ static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
// BLX and BX take one GPR reg. // BLX and BX take one GPR reg.
if (Opcode == ARM::BLX || Opcode == ARM::BLX_pred || if (Opcode == ARM::BLX || Opcode == ARM::BLX_pred ||
Opcode == ARM::BX) { Opcode == ARM::BX || Opcode == ARM::BX_pred) {
assert(NumOps >= 1 && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID && assert(NumOps >= 1 && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
"Reg operand expected"); "Reg operand expected");
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,

3
test/MC/Disassembler/ARM/arm-tests.txt
View File

@@ -164,6 +164,9 @@
# CHECK: bx r12 # CHECK: bx r12
0x1c 0xff 0x2f 0xe1 0x1c 0xff 0x2f 0xe1
# CHECK: bxeq r5
0x15 0xff 0x2f 0x01
# CHECK: uqadd16mi r6, r11, r8 # CHECK: uqadd16mi r6, r11, r8
0x18 0x60 0x6b 0x46 0x18 0x60 0x6b 0x46