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https://github.com/c64scene-ar/llvm-6502.git
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Fix indentation and wrap code at 80 cols
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15107 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman
parent
d3014edc51
commit
75fa4e4f99
@ -43,133 +43,123 @@
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using namespace llvm;
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namespace {
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Statistic<> numTwoAddressInstrs("twoaddressinstruction",
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"Number of two-address instructions");
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Statistic<> numInstrsAdded("twoaddressinstruction",
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"Number of instructions added");
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Statistic<> numTwoAddressInstrs("twoaddressinstruction",
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"Number of two-address instructions");
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Statistic<> numInstrsAdded("twoaddressinstruction",
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"Number of instructions added");
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struct TwoAddressInstructionPass : public MachineFunctionPass
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{
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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struct TwoAddressInstructionPass : public MachineFunctionPass {
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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/// runOnMachineFunction - pass entry point
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bool runOnMachineFunction(MachineFunction&);
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};
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/// runOnMachineFunction - pass entry point
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bool runOnMachineFunction(MachineFunction&);
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};
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RegisterPass<TwoAddressInstructionPass> X(
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"twoaddressinstruction", "Two-Address instruction pass");
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RegisterPass<TwoAddressInstructionPass>
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X("twoaddressinstruction", "Two-Address instruction pass");
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};
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const PassInfo *llvm::TwoAddressInstructionPassID = X.getPassInfo();
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void TwoAddressInstructionPass::getAnalysisUsage(AnalysisUsage &AU) const
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{
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AU.addPreserved<LiveVariables>();
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AU.addPreservedID(PHIEliminationID);
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MachineFunctionPass::getAnalysisUsage(AU);
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void TwoAddressInstructionPass::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addPreserved<LiveVariables>();
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AU.addPreservedID(PHIEliminationID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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/// runOnMachineFunction - Reduce two-address instructions to two
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/// operands.
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///
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bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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DEBUG(std::cerr << "Machine Function\n");
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const TargetMachine &TM = MF.getTarget();
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const MRegisterInfo &MRI = *TM.getRegisterInfo();
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const TargetInstrInfo &TII = *TM.getInstrInfo();
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LiveVariables* LV = getAnalysisToUpdate<LiveVariables>();
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DEBUG(std::cerr << "Machine Function\n");
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const TargetMachine &TM = MF.getTarget();
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const MRegisterInfo &MRI = *TM.getRegisterInfo();
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const TargetInstrInfo &TII = *TM.getInstrInfo();
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LiveVariables* LV = getAnalysisToUpdate<LiveVariables>();
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bool MadeChange = false;
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bool MadeChange = false;
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DEBUG(std::cerr << "********** REWRITING TWO-ADDR INSTRS **********\n");
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DEBUG(std::cerr << "********** Function: "
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<< MF.getFunction()->getName() << '\n');
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DEBUG(std::cerr << "********** REWRITING TWO-ADDR INSTRS **********\n");
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DEBUG(std::cerr << "********** Function: "
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<< MF.getFunction()->getName() << '\n');
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for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
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mbbi != mbbe; ++mbbi) {
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for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
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mi != me; ++mi) {
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unsigned opcode = mi->getOpcode();
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for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
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mbbi != mbbe; ++mbbi) {
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for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
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mi != me; ++mi) {
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unsigned opcode = mi->getOpcode();
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// ignore if it is not a two-address instruction
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if (!TII.isTwoAddrInstr(opcode))
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continue;
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// ignore if it is not a two-address instruction
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if (!TII.isTwoAddrInstr(opcode))
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continue;
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++numTwoAddressInstrs;
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++numTwoAddressInstrs;
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DEBUG(std::cerr << '\t'; mi->print(std::cerr, &TM));
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assert(mi->getOperand(1).isRegister() && mi->getOperand(1).getReg() &&
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mi->getOperand(1).isUse() && "two address instruction invalid");
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DEBUG(std::cerr << '\t'; mi->print(std::cerr, &TM));
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// if the two operands are the same we just remove the use
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// and mark the def as def&use, otherwise we have to insert a copy.
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if (mi->getOperand(0).getReg() != mi->getOperand(1).getReg()) {
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// rewrite:
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// a = b op c
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// to:
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// a = b
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// a = a op c
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unsigned regA = mi->getOperand(0).getReg();
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unsigned regB = mi->getOperand(1).getReg();
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assert(mi->getOperand(1).isRegister() &&
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mi->getOperand(1).getReg() &&
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mi->getOperand(1).isUse() &&
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"two address instruction invalid");
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assert(MRegisterInfo::isVirtualRegister(regA) &&
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MRegisterInfo::isVirtualRegister(regB) &&
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"cannot update physical register live information");
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// if the two operands are the same we just remove the use
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// and mark the def as def&use, otherwise we have to insert a copy.
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if (mi->getOperand(0).getReg() != mi->getOperand(1).getReg()) {
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// rewrite:
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// a = b op c
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// to:
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// a = b
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// a = a op c
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unsigned regA = mi->getOperand(0).getReg();
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unsigned regB = mi->getOperand(1).getReg();
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assert(MRegisterInfo::isVirtualRegister(regA) &&
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MRegisterInfo::isVirtualRegister(regB) &&
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"cannot update physical register live information");
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// first make sure we do not have a use of a in the
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// instruction (a = b + a for example) because our
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// transformation will not work. This should never occur
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// because we are in SSA form.
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// first make sure we do not have a use of a in the
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// instruction (a = b + a for example) because our
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// transformation will not work. This should never occur
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// because we are in SSA form.
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#ifndef NDEBUG
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for (unsigned i = 1; i != mi->getNumOperands(); ++i)
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assert(!mi->getOperand(i).isRegister() ||
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mi->getOperand(i).getReg() != regA);
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for (unsigned i = 1; i != mi->getNumOperands(); ++i)
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assert(!mi->getOperand(i).isRegister() ||
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mi->getOperand(i).getReg() != regA);
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#endif
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const TargetRegisterClass* rc =
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MF.getSSARegMap()->getRegClass(regA);
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unsigned Added = MRI.copyRegToReg(*mbbi, mi, regA, regB, rc);
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numInstrsAdded += Added;
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const TargetRegisterClass* rc = MF.getSSARegMap()->getRegClass(regA);
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unsigned Added = MRI.copyRegToReg(*mbbi, mi, regA, regB, rc);
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numInstrsAdded += Added;
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MachineBasicBlock::iterator prevMi = prior(mi);
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DEBUG(std::cerr << "\t\tprepend:\t";
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prevMi->print(std::cerr, &TM));
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MachineBasicBlock::iterator prevMi = prior(mi);
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DEBUG(std::cerr << "\t\tprepend:\t"; prevMi->print(std::cerr, &TM));
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if (LV) {
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// update live variables for regA
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assert(Added == 1 &&
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"Cannot handle multi-instruction copies yet!");
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LiveVariables::VarInfo& varInfo = LV->getVarInfo(regA);
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varInfo.DefInst = prevMi;
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if (LV) {
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// update live variables for regA
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assert(Added == 1 && "Cannot handle multi-instruction copies yet!");
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LiveVariables::VarInfo& varInfo = LV->getVarInfo(regA);
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varInfo.DefInst = prevMi;
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// update live variables for regB
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if (LV->removeVirtualRegisterKilled(regB, mbbi, mi))
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LV->addVirtualRegisterKilled(regB, prevMi);
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// update live variables for regB
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if (LV->removeVirtualRegisterKilled(regB, mbbi, mi))
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LV->addVirtualRegisterKilled(regB, prevMi);
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if (LV->removeVirtualRegisterDead(regB, mbbi, mi))
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LV->addVirtualRegisterDead(regB, prevMi);
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}
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// replace all occurences of regB with regA
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for (unsigned i = 1, e = mi->getNumOperands(); i != e; ++i) {
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if (mi->getOperand(i).isRegister() &&
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mi->getOperand(i).getReg() == regB)
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mi->SetMachineOperandReg(i, regA);
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}
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}
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assert(mi->getOperand(0).isDef());
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mi->getOperand(0).setUse();
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mi->RemoveOperand(1);
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MadeChange = true;
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DEBUG(std::cerr << "\t\trewrite to:\t";
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mi->print(std::cerr, &TM));
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if (LV->removeVirtualRegisterDead(regB, mbbi, mi))
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LV->addVirtualRegisterDead(regB, prevMi);
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}
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}
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return MadeChange;
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// replace all occurences of regB with regA
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for (unsigned i = 1, e = mi->getNumOperands(); i != e; ++i) {
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if (mi->getOperand(i).isRegister() &&
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mi->getOperand(i).getReg() == regB)
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mi->SetMachineOperandReg(i, regA);
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}
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}
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assert(mi->getOperand(0).isDef());
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mi->getOperand(0).setUse();
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mi->RemoveOperand(1);
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MadeChange = true;
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DEBUG(std::cerr << "\t\trewrite to:\t"; mi->print(std::cerr, &TM));
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}
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}
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return MadeChange;
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}
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