6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-16 14:31:59 +00:00
Code Issues Projects Releases Wiki Activity

Fix LDM_RET schedule itinery.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113435 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2010-09-08 22:57:08 +00:00
parent 90b54547d9
commit 7602acbf3b
5 changed files with 19 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/ARM/ARMInstrInfo.td
View File

@ -940,7 +940,7 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
hasExtraDefRegAllocReq = 1 in hasExtraDefRegAllocReq = 1 in
def LDM_RET : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, def LDM_RET : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
reglist:$dsts, variable_ops), reglist:$dsts, variable_ops),
IndexModeUpd, LdStMulFrm, IIC_Br, IndexModeUpd, LdStMulFrm, IIC_iLoadmBr,
"ldm${addr:submode}${p}\t$addr!, $dsts", "ldm${addr:submode}${p}\t$addr!, $dsts",
"$addr.addr = $wb", []>; "$addr.addr = $wb", []>;

3
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -2454,7 +2454,8 @@ let Defs =
let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
hasExtraDefRegAllocReq = 1 in hasExtraDefRegAllocReq = 1 in
def t2LDM_RET : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, def t2LDM_RET : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
reglist:$dsts, variable_ops), IIC_Br, reglist:$dsts, variable_ops),
IIC_iLoadmBr,
"ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts", "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts",
"$addr.addr = $wb", []> { "$addr.addr = $wb", []> {
let Inst{31-27} = 0b11101; let Inst{31-27} = 0b11101;

1
lib/Target/ARM/ARMSchedule.td
View File

@ -43,6 +43,7 @@ def IIC_iLoadiu : InstrItinClass;
def IIC_iLoadru : InstrItinClass; def IIC_iLoadru : InstrItinClass;
def IIC_iLoadsiu : InstrItinClass; def IIC_iLoadsiu : InstrItinClass;
def IIC_iLoadm : InstrItinClass; def IIC_iLoadm : InstrItinClass;
def IIC_iLoadmBr : InstrItinClass;
def IIC_iStorei : InstrItinClass; def IIC_iStorei : InstrItinClass;
def IIC_iStorer : InstrItinClass; def IIC_iStorer : InstrItinClass;
def IIC_iStoresi : InstrItinClass; def IIC_iStoresi : InstrItinClass;

9
lib/Target/ARM/ARMScheduleA8.td
View File

@ -122,6 +122,15 @@ def CortexA8Itineraries : ProcessorItineraries<
InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
InstrStage<1, [A8_LdSt0]>]>, InstrStage<1, [A8_LdSt0]>]>,
//
// Load multiple plus branch
InstrItinData<IIC_iLoadmBr , [InstrStage<2, [A8_Issue], 0>,
InstrStage<2, [A8_Pipe0], 0>,
InstrStage<2, [A8_Pipe1]>,
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
InstrStage<1, [A8_LdSt0]>,
InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
// Integer store pipeline // Integer store pipeline
// //
// use A8_Issue to enforce the 1 load/store per cycle limit // use A8_Issue to enforce the 1 load/store per cycle limit

6
lib/Target/ARM/ARMScheduleA9.td
View File

@ -107,6 +107,12 @@ def CortexA9Itineraries : ProcessorItineraries<
InstrItinData<IIC_iLoadm , [InstrStage<1, [A9_Pipe1]>, InstrItinData<IIC_iLoadm , [InstrStage<1, [A9_Pipe1]>,
InstrStage<1, [A9_LSPipe]>]>, InstrStage<1, [A9_LSPipe]>]>,
//
// Load multiple plus branch
InstrItinData<IIC_iLoadmBr , [InstrStage<1, [A9_Pipe1]>,
InstrStage<1, [A9_LSPipe]>,
InstrStage<1, [A9_Pipe0, A9_Pipe1]>]>,
// Integer store pipeline // Integer store pipeline
/// ///
// Immediate offset // Immediate offset