6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-31 10:34:17 +00:00
Code Issues Projects Releases Wiki Activity

Cleanup sloppy code. Jakob's review.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162825 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2012-08-29 04:41:37 +00:00
parent 2b70dfaaeb
commit 7611a88b58
1 changed files with 3 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -683,7 +683,7 @@ void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
// Handle register classes that require multiple instructions. // Handle register classes that require multiple instructions.
unsigned BeginIdx = 0; unsigned BeginIdx = 0;
unsigned SubRegs = 0; unsigned SubRegs = 0;
unsigned Spacing = 1; int Spacing = 1;
// Use VORRq when possible. // Use VORRq when possible.
if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
@ -705,8 +705,7 @@ void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg))
Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4, Spacing = 2; Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4, Spacing = 2;
if (!Opc) assert(Opc && "Impossible reg-to-reg copy");
llvm_unreachable("Impossible reg-to-reg copy");
const TargetRegisterInfo *TRI = &getRegisterInfo(); const TargetRegisterInfo *TRI = &getRegisterInfo();
MachineInstrBuilder Mov; MachineInstrBuilder Mov;
@ -724,8 +723,8 @@ void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i*Spacing); unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i*Spacing);
assert(Dst && Src && "Bad sub-register"); assert(Dst && Src && "Bad sub-register");
#ifndef NDEBUG #ifndef NDEBUG
DstRegs.insert(Dst);
assert(!DstRegs.count(Src) && "destructive vector copy"); assert(!DstRegs.count(Src) && "destructive vector copy");
DstRegs.insert(Dst);
#endif #endif
Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst) Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst)
.addReg(Src); .addReg(Src);