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Revert "Use std::bitset for SubtargetFeatures"

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This reverts commit r233055.

It still causes buildbot failures (gcc running out of memory on several platforms, and a self-host failure on arm), although less than the previous time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233068 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Michael Kuperstein
2015-03-24 12:56:59 +00:00
parent 9990bb34aa
commit 765aab84d6
33 changed files with 308 additions and 348 deletions
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71
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@@ -431,7 +431,7 @@ DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
raw_ostream &CS) const {
CommentStream = &CS;
assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
"Asked to disassemble an ARM instruction but Subtarget is in Thumb "
"mode!");
@@ -696,7 +696,7 @@ DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
raw_ostream &CS) const {
CommentStream = &CS;
assert(STI.getFeatureBits()[ARM::ModeThumb] &&
assert((STI.getFeatureBits() & ARM::ModeThumb) &&
"Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
// We want to read exactly 2 bytes of data.
@@ -1022,10 +1022,9 @@ static const uint16_t DPRDecoderTable[] = {
static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) {
const FeatureBitset &featureBits =
((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
bool hasD16 = featureBits[ARM::FeatureD16];
uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
.getFeatureBits();
bool hasD16 = featureBits & ARM::FeatureD16;
if (RegNo > 31 || (hasD16 && RegNo > 15))
return MCDisassembler::Fail;
@@ -1370,9 +1369,9 @@ static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
break;
}
const FeatureBitset &featureBits =
((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
if (featureBits[ARM::HasV8Ops] && (coproc != 14))
uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
.getFeatureBits();
if ((featureBits & ARM::HasV8Ops) && (coproc != 14))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(coproc));
@@ -3268,11 +3267,10 @@ static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
unsigned Rt = fieldFromInstruction(Insn, 12, 4);
unsigned Rn = fieldFromInstruction(Insn, 16, 4);
const FeatureBitset &featureBits =
((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
bool hasMP = featureBits[ARM::FeatureMP];
bool hasV7Ops = featureBits[ARM::HasV7Ops];
uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
.getFeatureBits();
bool hasMP = featureBits & ARM::FeatureMP;
bool hasV7Ops = featureBits & ARM::HasV7Ops;
if (Rn == 15) {
switch (Inst.getOpcode()) {
@@ -3355,11 +3353,10 @@ static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
imm |= (Rn << 9);
unsigned add = fieldFromInstruction(Insn, 9, 1);
const FeatureBitset &featureBits =
((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
bool hasMP = featureBits[ARM::FeatureMP];
bool hasV7Ops = featureBits[ARM::HasV7Ops];
uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
.getFeatureBits();
bool hasMP = featureBits & ARM::FeatureMP;
bool hasV7Ops = featureBits & ARM::HasV7Ops;
if (Rn == 15) {
switch (Inst.getOpcode()) {
@@ -3436,11 +3433,10 @@ static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
unsigned imm = fieldFromInstruction(Insn, 0, 12);
imm |= (Rn << 13);
const FeatureBitset &featureBits =
((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
bool hasMP = featureBits[ARM::FeatureMP];
bool hasV7Ops = featureBits[ARM::HasV7Ops];
uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
.getFeatureBits();
bool hasMP = (featureBits & ARM::FeatureMP);
bool hasV7Ops = (featureBits & ARM::HasV7Ops);
if (Rn == 15) {
switch (Inst.getOpcode()) {
@@ -3554,10 +3550,9 @@ static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
unsigned U = fieldFromInstruction(Insn, 23, 1);
int imm = fieldFromInstruction(Insn, 0, 12);
const FeatureBitset &featureBits =
((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
bool hasV7Ops = featureBits[ARM::HasV7Ops];
uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
.getFeatureBits();
bool hasV7Ops = (featureBits & ARM::HasV7Ops);
if (Rt == 15) {
switch (Inst.getOpcode()) {
@@ -3878,10 +3873,9 @@ static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
if (Val == 0xA || Val == 0xB)
return MCDisassembler::Fail;
const FeatureBitset &featureBits =
((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
.getFeatureBits();
if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(Val));
@@ -4031,10 +4025,9 @@ static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success;
const FeatureBitset &FeatureBits =
((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
if (FeatureBits[ARM::FeatureMClass]) {
uint64_t FeatureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
.getFeatureBits();
if (FeatureBits & ARM::FeatureMClass) {
unsigned ValLow = Val & 0xff;
// Validate the SYSm value first.
@@ -4054,7 +4047,7 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
case 17: // basepri
case 18: // basepri_max
case 19: // faultmask
if (!(FeatureBits[ARM::HasV7Ops]))
if (!(FeatureBits & ARM::HasV7Ops))
// Values basepri, basepri_max and faultmask are only valid for v7m.
return MCDisassembler::Fail;
break;
@@ -4064,7 +4057,7 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
if (Inst.getOpcode() == ARM::t2MSR_M) {
unsigned Mask = fieldFromInstruction(Val, 10, 2);
if (!(FeatureBits[ARM::HasV7Ops])) {
if (!(FeatureBits & ARM::HasV7Ops)) {
// The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
// unpredictable.
if (Mask != 2)
@@ -4078,7 +4071,7 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
// indicates the move for the GE{3:0} bits, the mask{0} bit can be set
// only if the processor includes the DSP extension.
if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
(!(FeatureBits[ARM::FeatureDSPThumb2]) && (Mask & 1)))
(!(FeatureBits & ARM::FeatureDSPThumb2) && (Mask & 1)))
S = MCDisassembler::SoftFail;
}
}