mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Rename members to match LLVM naming conventions more closely.
Remove the unused reserved_ bit vector, no functional change intended. This doesn't break 'svn blame', this file really is all my fault. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127607 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
e2189144d4
commit
766faf4b2b
@ -31,24 +31,23 @@ using namespace llvm;
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namespace {
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class InlineSpiller : public Spiller {
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MachineFunctionPass &pass_;
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MachineFunction &mf_;
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LiveIntervals &lis_;
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LiveStacks &lss_;
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AliasAnalysis *aa_;
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VirtRegMap &vrm_;
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MachineFrameInfo &mfi_;
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MachineRegisterInfo &mri_;
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const TargetInstrInfo &tii_;
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const TargetRegisterInfo &tri_;
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const BitVector reserved_;
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MachineFunctionPass &Pass;
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MachineFunction &MF;
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LiveIntervals &LIS;
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LiveStacks &LSS;
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AliasAnalysis *AA;
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VirtRegMap &VRM;
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MachineFrameInfo &MFI;
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MachineRegisterInfo &MRI;
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const TargetInstrInfo &TII;
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const TargetRegisterInfo &TRI;
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// Variables that are valid during spill(), but used by multiple methods.
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LiveRangeEdit *edit_;
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const TargetRegisterClass *rc_;
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int stackSlot_;
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LiveRangeEdit *Edit;
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const TargetRegisterClass *RC;
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int StackSlot;
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// All registers to spill to stackSlot_, including the main register.
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// All registers to spill to StackSlot, including the main register.
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SmallVector<unsigned, 8> RegsToSpill;
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// All COPY instructions to/from snippets.
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@ -56,7 +55,7 @@ class InlineSpiller : public Spiller {
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SmallPtrSet<MachineInstr*, 8> SnippetCopies;
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// Values that failed to remat at some point.
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SmallPtrSet<VNInfo*, 8> usedValues_;
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SmallPtrSet<VNInfo*, 8> UsedValues;
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~InlineSpiller() {}
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@ -64,17 +63,16 @@ public:
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InlineSpiller(MachineFunctionPass &pass,
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MachineFunction &mf,
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VirtRegMap &vrm)
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: pass_(pass),
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mf_(mf),
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lis_(pass.getAnalysis<LiveIntervals>()),
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lss_(pass.getAnalysis<LiveStacks>()),
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aa_(&pass.getAnalysis<AliasAnalysis>()),
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vrm_(vrm),
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mfi_(*mf.getFrameInfo()),
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mri_(mf.getRegInfo()),
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tii_(*mf.getTarget().getInstrInfo()),
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tri_(*mf.getTarget().getRegisterInfo()),
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reserved_(tri_.getReservedRegs(mf_)) {}
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: Pass(pass),
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MF(mf),
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LIS(pass.getAnalysis<LiveIntervals>()),
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LSS(pass.getAnalysis<LiveStacks>()),
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AA(&pass.getAnalysis<AliasAnalysis>()),
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VRM(vrm),
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MFI(*mf.getFrameInfo()),
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MRI(mf.getRegInfo()),
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TII(*mf.getTarget().getInstrInfo()),
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TRI(*mf.getTarget().getRegisterInfo()) {}
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void spill(LiveRangeEdit &);
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@ -135,9 +133,9 @@ static unsigned isFullCopyOf(const MachineInstr *MI, unsigned Reg) {
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/// isSnippet - Identify if a live interval is a snippet that should be spilled.
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/// It is assumed that SnipLI is a virtual register with the same original as
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/// edit_->getReg().
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/// Edit->getReg().
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bool InlineSpiller::isSnippet(const LiveInterval &SnipLI) {
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unsigned Reg = edit_->getReg();
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unsigned Reg = Edit->getReg();
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// A snippet is a tiny live range with only a single instruction using it
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// besides copies to/from Reg or spills/fills. We accept:
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@ -146,14 +144,14 @@ bool InlineSpiller::isSnippet(const LiveInterval &SnipLI) {
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// %snip = USE %snip
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// %Reg = COPY %snip / SPILL %snip, fi#
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//
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if (SnipLI.getNumValNums() > 2 || !lis_.intervalIsInOneMBB(SnipLI))
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if (SnipLI.getNumValNums() > 2 || !LIS.intervalIsInOneMBB(SnipLI))
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return false;
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MachineInstr *UseMI = 0;
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// Check that all uses satisfy our criteria.
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for (MachineRegisterInfo::reg_nodbg_iterator
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RI = mri_.reg_nodbg_begin(SnipLI.reg);
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RI = MRI.reg_nodbg_begin(SnipLI.reg);
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MachineInstr *MI = RI.skipInstruction();) {
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// Allow copies to/from Reg.
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@ -162,11 +160,11 @@ bool InlineSpiller::isSnippet(const LiveInterval &SnipLI) {
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// Allow stack slot loads.
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int FI;
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if (SnipLI.reg == tii_.isLoadFromStackSlot(MI, FI) && FI == stackSlot_)
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if (SnipLI.reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot)
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continue;
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// Allow stack slot stores.
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if (SnipLI.reg == tii_.isStoreToStackSlot(MI, FI) && FI == stackSlot_)
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if (SnipLI.reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot)
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continue;
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// Allow a single additional instruction.
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@ -180,8 +178,8 @@ bool InlineSpiller::isSnippet(const LiveInterval &SnipLI) {
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/// collectRegsToSpill - Collect live range snippets that only have a single
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/// real use.
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void InlineSpiller::collectRegsToSpill() {
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unsigned Reg = edit_->getReg();
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unsigned Orig = vrm_.getOriginal(Reg);
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unsigned Reg = Edit->getReg();
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unsigned Orig = VRM.getOriginal(Reg);
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// Main register always spills.
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RegsToSpill.assign(1, Reg);
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@ -192,16 +190,16 @@ void InlineSpiller::collectRegsToSpill() {
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if (Orig == Reg)
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return;
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for (MachineRegisterInfo::reg_iterator RI = mri_.reg_begin(Reg);
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for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Reg);
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MachineInstr *MI = RI.skipInstruction();) {
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unsigned SnipReg = isFullCopyOf(MI, Reg);
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if (!SnipReg)
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continue;
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if (!TargetRegisterInfo::isVirtualRegister(SnipReg))
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continue;
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if (vrm_.getOriginal(SnipReg) != Orig)
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if (VRM.getOriginal(SnipReg) != Orig)
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continue;
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LiveInterval &SnipLI = lis_.getInterval(SnipReg);
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LiveInterval &SnipLI = LIS.getInterval(SnipReg);
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if (!isSnippet(SnipLI))
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continue;
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SnippetCopies.insert(MI);
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@ -215,14 +213,14 @@ void InlineSpiller::collectRegsToSpill() {
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/// reMaterializeFor - Attempt to rematerialize before MI instead of reloading.
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bool InlineSpiller::reMaterializeFor(MachineBasicBlock::iterator MI) {
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SlotIndex UseIdx = lis_.getInstructionIndex(MI).getUseIndex();
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VNInfo *OrigVNI = edit_->getParent().getVNInfoAt(UseIdx);
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SlotIndex UseIdx = LIS.getInstructionIndex(MI).getUseIndex();
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VNInfo *OrigVNI = Edit->getParent().getVNInfoAt(UseIdx);
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if (!OrigVNI) {
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DEBUG(dbgs() << "\tadding <undef> flags: ");
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.isUse() && MO.getReg() == edit_->getReg())
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if (MO.isReg() && MO.isUse() && MO.getReg() == Edit->getReg())
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MO.setIsUndef();
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}
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DEBUG(dbgs() << UseIdx << '\t' << *MI);
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@ -231,27 +229,27 @@ bool InlineSpiller::reMaterializeFor(MachineBasicBlock::iterator MI) {
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// FIXME: Properly remat for snippets as well.
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if (SnippetCopies.count(MI)) {
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usedValues_.insert(OrigVNI);
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UsedValues.insert(OrigVNI);
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return false;
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}
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LiveRangeEdit::Remat RM(OrigVNI);
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if (!edit_->canRematerializeAt(RM, UseIdx, false, lis_)) {
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usedValues_.insert(OrigVNI);
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if (!Edit->canRematerializeAt(RM, UseIdx, false, LIS)) {
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UsedValues.insert(OrigVNI);
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DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI);
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return false;
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}
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// If the instruction also writes edit_->getReg(), it had better not require
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// If the instruction also writes Edit->getReg(), it had better not require
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// the same register for uses and defs.
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bool Reads, Writes;
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SmallVector<unsigned, 8> Ops;
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tie(Reads, Writes) = MI->readsWritesVirtualRegister(edit_->getReg(), &Ops);
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tie(Reads, Writes) = MI->readsWritesVirtualRegister(Edit->getReg(), &Ops);
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if (Writes) {
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for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(Ops[i]);
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if (MO.isUse() ? MI->isRegTiedToDefOperand(Ops[i]) : MO.getSubReg()) {
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usedValues_.insert(OrigVNI);
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UsedValues.insert(OrigVNI);
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DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI);
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return false;
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}
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@ -262,35 +260,35 @@ bool InlineSpiller::reMaterializeFor(MachineBasicBlock::iterator MI) {
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// fold a load into the instruction. That avoids allocating a new register.
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if (RM.OrigMI->getDesc().canFoldAsLoad() &&
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foldMemoryOperand(MI, Ops, RM.OrigMI)) {
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edit_->markRematerialized(RM.ParentVNI);
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Edit->markRematerialized(RM.ParentVNI);
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return true;
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}
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// Alocate a new register for the remat.
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LiveInterval &NewLI = edit_->create(mri_, lis_, vrm_);
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LiveInterval &NewLI = Edit->create(MRI, LIS, VRM);
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NewLI.markNotSpillable();
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// Rematting for a copy: Set allocation hint to be the destination register.
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if (MI->isCopy())
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mri_.setRegAllocationHint(NewLI.reg, 0, MI->getOperand(0).getReg());
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MRI.setRegAllocationHint(NewLI.reg, 0, MI->getOperand(0).getReg());
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// Finally we can rematerialize OrigMI before MI.
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SlotIndex DefIdx = edit_->rematerializeAt(*MI->getParent(), MI, NewLI.reg, RM,
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lis_, tii_, tri_);
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SlotIndex DefIdx = Edit->rematerializeAt(*MI->getParent(), MI, NewLI.reg, RM,
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LIS, TII, TRI);
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DEBUG(dbgs() << "\tremat: " << DefIdx << '\t'
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<< *lis_.getInstructionFromIndex(DefIdx));
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<< *LIS.getInstructionFromIndex(DefIdx));
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// Replace operands
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for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(Ops[i]);
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if (MO.isReg() && MO.isUse() && MO.getReg() == edit_->getReg()) {
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if (MO.isReg() && MO.isUse() && MO.getReg() == Edit->getReg()) {
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MO.setReg(NewLI.reg);
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MO.setIsKill();
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}
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}
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DEBUG(dbgs() << "\t " << UseIdx << '\t' << *MI);
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VNInfo *DefVNI = NewLI.getNextValue(DefIdx, 0, lis_.getVNInfoAllocator());
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VNInfo *DefVNI = NewLI.getNextValue(DefIdx, 0, LIS.getVNInfoAllocator());
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NewLI.addRange(LiveRange(DefIdx, UseIdx.getDefIndex(), DefVNI));
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DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
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return true;
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@ -300,15 +298,15 @@ bool InlineSpiller::reMaterializeFor(MachineBasicBlock::iterator MI) {
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/// and trim the live ranges after.
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void InlineSpiller::reMaterializeAll() {
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// Do a quick scan of the interval values to find if any are remattable.
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if (!edit_->anyRematerializable(lis_, tii_, aa_))
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if (!Edit->anyRematerializable(LIS, TII, AA))
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return;
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usedValues_.clear();
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UsedValues.clear();
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// Try to remat before all uses of edit_->getReg().
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// Try to remat before all uses of Edit->getReg().
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bool anyRemat = false;
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for (MachineRegisterInfo::use_nodbg_iterator
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RI = mri_.use_nodbg_begin(edit_->getReg());
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RI = MRI.use_nodbg_begin(Edit->getReg());
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MachineInstr *MI = RI.skipInstruction();)
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anyRemat |= reMaterializeFor(MI);
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@ -317,16 +315,16 @@ void InlineSpiller::reMaterializeAll() {
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// Remove any values that were completely rematted.
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bool anyRemoved = false;
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for (LiveInterval::vni_iterator I = edit_->getParent().vni_begin(),
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E = edit_->getParent().vni_end(); I != E; ++I) {
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for (LiveInterval::vni_iterator I = Edit->getParent().vni_begin(),
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E = Edit->getParent().vni_end(); I != E; ++I) {
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VNInfo *VNI = *I;
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if (VNI->hasPHIKill() || !edit_->didRematerialize(VNI) ||
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usedValues_.count(VNI))
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if (VNI->hasPHIKill() || !Edit->didRematerialize(VNI) ||
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UsedValues.count(VNI))
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continue;
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MachineInstr *DefMI = lis_.getInstructionFromIndex(VNI->def);
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MachineInstr *DefMI = LIS.getInstructionFromIndex(VNI->def);
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DEBUG(dbgs() << "\tremoving dead def: " << VNI->def << '\t' << *DefMI);
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lis_.RemoveMachineInstrFromMaps(DefMI);
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vrm_.RemoveMachineInstrFromMaps(DefMI);
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LIS.RemoveMachineInstrFromMaps(DefMI);
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VRM.RemoveMachineInstrFromMaps(DefMI);
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DefMI->eraseFromParent();
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VNI->def = SlotIndex();
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anyRemoved = true;
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@ -336,17 +334,17 @@ void InlineSpiller::reMaterializeAll() {
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return;
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// Removing values may cause debug uses where parent is not live.
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for (MachineRegisterInfo::use_iterator RI = mri_.use_begin(edit_->getReg());
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for (MachineRegisterInfo::use_iterator RI = MRI.use_begin(Edit->getReg());
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MachineInstr *MI = RI.skipInstruction();) {
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if (!MI->isDebugValue())
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continue;
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// Try to preserve the debug value if parent is live immediately after it.
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MachineBasicBlock::iterator NextMI = MI;
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++NextMI;
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if (NextMI != MI->getParent()->end() && !lis_.isNotInMIMap(NextMI)) {
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SlotIndex Idx = lis_.getInstructionIndex(NextMI);
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VNInfo *VNI = edit_->getParent().getVNInfoAt(Idx);
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if (VNI && (VNI->hasPHIKill() || usedValues_.count(VNI)))
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if (NextMI != MI->getParent()->end() && !LIS.isNotInMIMap(NextMI)) {
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SlotIndex Idx = LIS.getInstructionIndex(NextMI);
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VNInfo *VNI = Edit->getParent().getVNInfoAt(Idx);
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if (VNI && (VNI->hasPHIKill() || UsedValues.count(VNI)))
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continue;
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}
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DEBUG(dbgs() << "Removing debug info due to remat:" << "\t" << *MI);
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@ -354,20 +352,20 @@ void InlineSpiller::reMaterializeAll() {
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}
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}
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/// If MI is a load or store of stackSlot_, it can be removed.
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/// If MI is a load or store of StackSlot, it can be removed.
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bool InlineSpiller::coalesceStackAccess(MachineInstr *MI, unsigned Reg) {
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int FI = 0;
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unsigned InstrReg;
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if (!(InstrReg = tii_.isLoadFromStackSlot(MI, FI)) &&
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!(InstrReg = tii_.isStoreToStackSlot(MI, FI)))
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if (!(InstrReg = TII.isLoadFromStackSlot(MI, FI)) &&
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!(InstrReg = TII.isStoreToStackSlot(MI, FI)))
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return false;
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// We have a stack access. Is it the right register and slot?
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if (InstrReg != Reg || FI != stackSlot_)
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if (InstrReg != Reg || FI != StackSlot)
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return false;
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DEBUG(dbgs() << "Coalescing stack access: " << *MI);
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lis_.RemoveMachineInstrFromMaps(MI);
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LIS.RemoveMachineInstrFromMaps(MI);
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MI->eraseFromParent();
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return true;
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}
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@ -400,13 +398,13 @@ bool InlineSpiller::foldMemoryOperand(MachineBasicBlock::iterator MI,
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}
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MachineInstr *FoldMI =
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LoadMI ? tii_.foldMemoryOperand(MI, FoldOps, LoadMI)
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: tii_.foldMemoryOperand(MI, FoldOps, stackSlot_);
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LoadMI ? TII.foldMemoryOperand(MI, FoldOps, LoadMI)
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: TII.foldMemoryOperand(MI, FoldOps, StackSlot);
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if (!FoldMI)
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return false;
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lis_.ReplaceMachineInstrInMaps(MI, FoldMI);
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LIS.ReplaceMachineInstrInMaps(MI, FoldMI);
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if (!LoadMI)
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vrm_.addSpillSlotUse(stackSlot_, FoldMI);
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VRM.addSpillSlotUse(StackSlot, FoldMI);
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MI->eraseFromParent();
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DEBUG(dbgs() << "\tfolded: " << *FoldMI);
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return true;
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@ -416,14 +414,14 @@ bool InlineSpiller::foldMemoryOperand(MachineBasicBlock::iterator MI,
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void InlineSpiller::insertReload(LiveInterval &NewLI,
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MachineBasicBlock::iterator MI) {
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MachineBasicBlock &MBB = *MI->getParent();
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SlotIndex Idx = lis_.getInstructionIndex(MI).getDefIndex();
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tii_.loadRegFromStackSlot(MBB, MI, NewLI.reg, stackSlot_, rc_, &tri_);
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SlotIndex Idx = LIS.getInstructionIndex(MI).getDefIndex();
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TII.loadRegFromStackSlot(MBB, MI, NewLI.reg, StackSlot, RC, &TRI);
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--MI; // Point to load instruction.
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SlotIndex LoadIdx = lis_.InsertMachineInstrInMaps(MI).getDefIndex();
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vrm_.addSpillSlotUse(stackSlot_, MI);
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SlotIndex LoadIdx = LIS.InsertMachineInstrInMaps(MI).getDefIndex();
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VRM.addSpillSlotUse(StackSlot, MI);
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DEBUG(dbgs() << "\treload: " << LoadIdx << '\t' << *MI);
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VNInfo *LoadVNI = NewLI.getNextValue(LoadIdx, 0,
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lis_.getVNInfoAllocator());
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LIS.getVNInfoAllocator());
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NewLI.addRange(LiveRange(LoadIdx, Idx, LoadVNI));
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}
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@ -433,26 +431,26 @@ void InlineSpiller::insertSpill(LiveInterval &NewLI, const LiveInterval &OldLI,
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MachineBasicBlock &MBB = *MI->getParent();
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// Get the defined value. It could be an early clobber so keep the def index.
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SlotIndex Idx = lis_.getInstructionIndex(MI).getDefIndex();
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SlotIndex Idx = LIS.getInstructionIndex(MI).getDefIndex();
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VNInfo *VNI = OldLI.getVNInfoAt(Idx);
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assert(VNI && VNI->def.getDefIndex() == Idx && "Inconsistent VNInfo");
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Idx = VNI->def;
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tii_.storeRegToStackSlot(MBB, ++MI, NewLI.reg, true, stackSlot_, rc_, &tri_);
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TII.storeRegToStackSlot(MBB, ++MI, NewLI.reg, true, StackSlot, RC, &TRI);
|
||||
--MI; // Point to store instruction.
|
||||
SlotIndex StoreIdx = lis_.InsertMachineInstrInMaps(MI).getDefIndex();
|
||||
vrm_.addSpillSlotUse(stackSlot_, MI);
|
||||
SlotIndex StoreIdx = LIS.InsertMachineInstrInMaps(MI).getDefIndex();
|
||||
VRM.addSpillSlotUse(StackSlot, MI);
|
||||
DEBUG(dbgs() << "\tspilled: " << StoreIdx << '\t' << *MI);
|
||||
VNInfo *StoreVNI = NewLI.getNextValue(Idx, 0, lis_.getVNInfoAllocator());
|
||||
VNInfo *StoreVNI = NewLI.getNextValue(Idx, 0, LIS.getVNInfoAllocator());
|
||||
NewLI.addRange(LiveRange(Idx, StoreIdx, StoreVNI));
|
||||
}
|
||||
|
||||
/// spillAroundUses - insert spill code around each use of Reg.
|
||||
void InlineSpiller::spillAroundUses(unsigned Reg) {
|
||||
LiveInterval &OldLI = lis_.getInterval(Reg);
|
||||
LiveInterval &OldLI = LIS.getInterval(Reg);
|
||||
|
||||
// Iterate over instructions using Reg.
|
||||
for (MachineRegisterInfo::reg_iterator RI = mri_.reg_begin(Reg);
|
||||
for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Reg);
|
||||
MachineInstr *MI = RI.skipInstruction();) {
|
||||
|
||||
// Debug values are not allowed to affect codegen.
|
||||
@ -461,7 +459,7 @@ void InlineSpiller::spillAroundUses(unsigned Reg) {
|
||||
uint64_t Offset = MI->getOperand(1).getImm();
|
||||
const MDNode *MDPtr = MI->getOperand(2).getMetadata();
|
||||
DebugLoc DL = MI->getDebugLoc();
|
||||
if (MachineInstr *NewDV = tii_.emitFrameIndexDebugValue(mf_, stackSlot_,
|
||||
if (MachineInstr *NewDV = TII.emitFrameIndexDebugValue(MF, StackSlot,
|
||||
Offset, MDPtr, DL)) {
|
||||
DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI);
|
||||
MachineBasicBlock *MBB = MI->getParent();
|
||||
@ -492,7 +490,7 @@ void InlineSpiller::spillAroundUses(unsigned Reg) {
|
||||
|
||||
// Allocate interval around instruction.
|
||||
// FIXME: Infer regclass from instruction alone.
|
||||
LiveInterval &NewLI = edit_->create(mri_, lis_, vrm_);
|
||||
LiveInterval &NewLI = Edit->create(MRI, LIS, VRM);
|
||||
NewLI.markNotSpillable();
|
||||
|
||||
if (Reads)
|
||||
@ -521,42 +519,42 @@ void InlineSpiller::spillAroundUses(unsigned Reg) {
|
||||
}
|
||||
|
||||
void InlineSpiller::spill(LiveRangeEdit &edit) {
|
||||
edit_ = &edit;
|
||||
Edit = &edit;
|
||||
assert(!TargetRegisterInfo::isStackSlot(edit.getReg())
|
||||
&& "Trying to spill a stack slot.");
|
||||
DEBUG(dbgs() << "Inline spilling "
|
||||
<< mri_.getRegClass(edit.getReg())->getName()
|
||||
<< MRI.getRegClass(edit.getReg())->getName()
|
||||
<< ':' << edit.getParent() << "\nFrom original "
|
||||
<< PrintReg(vrm_.getOriginal(edit.getReg())) << '\n');
|
||||
<< PrintReg(VRM.getOriginal(edit.getReg())) << '\n');
|
||||
assert(edit.getParent().isSpillable() &&
|
||||
"Attempting to spill already spilled value.");
|
||||
|
||||
// Share a stack slot among all descendants of Orig.
|
||||
unsigned Orig = vrm_.getOriginal(edit.getReg());
|
||||
stackSlot_ = vrm_.getStackSlot(Orig);
|
||||
unsigned Orig = VRM.getOriginal(edit.getReg());
|
||||
StackSlot = VRM.getStackSlot(Orig);
|
||||
|
||||
collectRegsToSpill();
|
||||
|
||||
reMaterializeAll();
|
||||
|
||||
// Remat may handle everything.
|
||||
if (edit_->getParent().empty())
|
||||
if (Edit->getParent().empty())
|
||||
return;
|
||||
|
||||
rc_ = mri_.getRegClass(edit.getReg());
|
||||
RC = MRI.getRegClass(edit.getReg());
|
||||
|
||||
if (stackSlot_ == VirtRegMap::NO_STACK_SLOT)
|
||||
stackSlot_ = vrm_.assignVirt2StackSlot(Orig);
|
||||
if (StackSlot == VirtRegMap::NO_STACK_SLOT)
|
||||
StackSlot = VRM.assignVirt2StackSlot(Orig);
|
||||
|
||||
if (Orig != edit.getReg())
|
||||
vrm_.assignVirt2StackSlot(edit.getReg(), stackSlot_);
|
||||
VRM.assignVirt2StackSlot(edit.getReg(), StackSlot);
|
||||
|
||||
// Update LiveStacks now that we are committed to spilling.
|
||||
LiveInterval &stacklvr = lss_.getOrCreateInterval(stackSlot_, rc_);
|
||||
LiveInterval &stacklvr = LSS.getOrCreateInterval(StackSlot, RC);
|
||||
if (!stacklvr.hasAtLeastOneValue())
|
||||
stacklvr.getNextValue(SlotIndex(), 0, lss_.getVNInfoAllocator());
|
||||
stacklvr.getNextValue(SlotIndex(), 0, LSS.getVNInfoAllocator());
|
||||
for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
|
||||
stacklvr.MergeRangesInAsValue(lis_.getInterval(RegsToSpill[i]),
|
||||
stacklvr.MergeRangesInAsValue(LIS.getInterval(RegsToSpill[i]),
|
||||
stacklvr.getValNumInfo(0));
|
||||
|
||||
// Spill around uses of all RegsToSpill.
|
||||
@ -564,15 +562,15 @@ void InlineSpiller::spill(LiveRangeEdit &edit) {
|
||||
spillAroundUses(RegsToSpill[i]);
|
||||
|
||||
// Finally delete the SnippetCopies.
|
||||
for (MachineRegisterInfo::reg_iterator RI = mri_.reg_begin(edit.getReg());
|
||||
for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(edit.getReg());
|
||||
MachineInstr *MI = RI.skipInstruction();) {
|
||||
assert(SnippetCopies.count(MI) && "Remaining use wasn't a snippet copy");
|
||||
// FIXME: Do this with a LiveRangeEdit callback.
|
||||
vrm_.RemoveMachineInstrFromMaps(MI);
|
||||
lis_.RemoveMachineInstrFromMaps(MI);
|
||||
VRM.RemoveMachineInstrFromMaps(MI);
|
||||
LIS.RemoveMachineInstrFromMaps(MI);
|
||||
MI->eraseFromParent();
|
||||
}
|
||||
|
||||
for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
|
||||
edit.eraseVirtReg(RegsToSpill[i], lis_);
|
||||
edit.eraseVirtReg(RegsToSpill[i], LIS);
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user