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Remove the G8RC_NOX0_and_GPRC_NOR0 PPC register class
As Jakob pointed out in his review of r177423, having a shared ZERO register between the 32- and 64-bit register classes causes this odd G8RC_NOX0_and_GPRC_NOR0 class to be created. As recommended, this adds a ZERO8 register which differentiates the 32- and 64-bit zeros. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177683 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1042,7 +1042,8 @@ bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
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short Imm;
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if (isIntS16Immediate(CN, Imm)) {
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Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
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Base = DAG.getRegister(PPC::ZERO, CN->getValueType(0));
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Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
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CN->getValueType(0));
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return true;
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}
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@ -1090,7 +1091,8 @@ bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
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}
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// Otherwise, do it the hard way, using R0 as the base register.
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Base = DAG.getRegister(PPC::ZERO, N.getValueType());
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Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
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N.getValueType());
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Index = N;
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return true;
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}
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@ -1152,7 +1154,8 @@ bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
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short Imm;
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if (isIntS16Immediate(CN, Imm)) {
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Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
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Base = DAG.getRegister(PPC::ZERO, CN->getValueType(0));
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Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
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CN->getValueType(0));
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return true;
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}
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@ -5779,7 +5782,7 @@ PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
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// registers without caring whether they're 32 or 64, but here we're
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// doing actual arithmetic on the addresses.
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bool is64bit = PPCSubTarget.isPPC64();
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unsigned ZeroReg = PPC::ZERO;
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unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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MachineFunction *F = BB->getParent();
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@ -6397,7 +6400,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
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unsigned Ptr1Reg;
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unsigned TmpReg = RegInfo.createVirtualRegister(RC);
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unsigned ZeroReg = PPC::ZERO;
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unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
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// thisMBB:
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// ...
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// fallthrough --> loopMBB
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@ -125,6 +125,7 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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// The ZERO register is not really a register, but the representation of r0
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// when used in instructions that treat r0 as the constant 0.
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Reserved.set(PPC::ZERO);
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Reserved.set(PPC::ZERO8);
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// The FP register is also not really a register, but is the representation
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// of the frame pointer register used by ISD::FRAMEADDR.
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@ -87,7 +87,8 @@ foreach Index = 0-31 in {
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}
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// The reprsentation of r0 when treated as the constant 0.
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def ZERO : GPR<0, "r0">;
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def ZERO : GPR<0, "r0">;
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def ZERO8 : GP8<ZERO, "r0">;
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// Representations of the frame pointer used by ISD::FRAMEADDR.
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def FP : GPR<0 /* arbitrary */, "**FRAME POINTER**">;
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@ -181,7 +182,7 @@ def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12),
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// the value in the r0 register), and we use these register subclasses to
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// prevent r0 from being allocated for use by those instructions.
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def GPRC_NOR0 : RegisterClass<"PPC", [i32], 32, (add (sub GPRC, R0), ZERO)>;
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def G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0), ZERO)>;
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def G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0), ZERO8)>;
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// Allocate volatiles first, then non-volatiles in reverse order. With the SVR4
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// ABI the size of the Floating-point register save area is determined by the
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