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[mips] Add negative tests confirm that supported ISA's don't allow instructions added in later ISA's

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Summary:
test/MC/Mips/<isa1>/invalid-<isa2>.s
    Test that <isa1> does not support <isa2>'s instructions.
test/MC/Mips/<isa1>/invalid-<isa2>-xfail.s
    Things that should be invalid but currently aren't. Will XPASS if any
    become invalid.

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3262

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205538 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
2014-04-03 14:14:22 +00:00
parent 8750f9a291
commit 769a6f2116
10 changed files with 146 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
test/MC/Mips/mips32/invalid-mips32r2-xfail.s Normal file
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@ -0,0 +1,19 @@
# Instructions that are supposed to be invalid but currently aren't
# This test will XPASS if any insn stops assembling.
#
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 \
# RUN: 2> %t1
# RUN: not FileCheck %s < %t1
# XFAIL: *
# CHECK-NOT: error
.set noat
cvt.l.d $f24,$f15
cvt.l.s $f11,$f29
di $s8
ei $t6
luxc1 $f19,$s6($s5)
mfhc1 $s8,$f24
mthc1 $zero,$f16
rdhwr $sp,$11
suxc1 $f12,$k1($t5)

17
test/MC/Mips/mips32/invalid-mips32r2.s
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@ -5,4 +5,19 @@
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
.set noat .set noat
pause # CHECK: requires a CPU feature not currently enabled ldxc1 $f8,$s7($t7) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
nmadd.d $f18,$f9,$f14,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
nmsub.d $f30,$f8,$f16,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
pause # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sdxc1 $f11,$t2($t6) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
seb $t9,$t7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
seh $v1,$t4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
swxc1 $f19,$t4($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
wsbh $k1,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

1
test/MC/Mips/mips32r2/valid.s
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@ -89,6 +89,7 @@
msub.d $f10,$f1,$f31,$f18 msub.d $f10,$f1,$f31,$f18
msub.s $f12,$f19,$f10,$f16 msub.s $f12,$f19,$f10,$f16
msubu $t7,$a1 msubu $t7,$a1
mtc0 $t1,$29,3
mtc1 $s8,$f9 mtc1 $s8,$f9
mthc1 $zero,$f16 mthc1 $zero,$f16
mthi $s1 mthi $s1

22
test/MC/Mips/mips4/invalid-mips64-xfail.s Normal file
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@ -0,0 +1,22 @@
# Instructions that are supposed to be invalid but currently aren't
# This test will XPASS if any insn stops assembling.
#
# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 \
# RUN: 2> %t1
# RUN: not FileCheck %s < %t1
# XFAIL: *
# CHECK-NOT: error
.set noat
deret
luxc1 $f19,$s6($s5)
madd $s6,$t5
madd $zero,$t1
maddu $s3,$gp
maddu $t8,$s2
mfc0 $a2,$14,1
msub $s7,$k1
msubu $t7,$a1
mtc0 $t1,$29,3
mul $s0,$s4,$at
suxc1 $f12,$k1($t5)

12
test/MC/Mips/mips4/invalid-mips64.s Normal file
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@ -0,0 +1,12 @@
# Instructions that are invalid
#
# FIXME: This test should be moved to the mips5 directory when mips5 is supported
# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 \
# RUN: 2>%t1
# RUN: FileCheck %s < %t1
.set noat
clo $t3,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

27
test/MC/Mips/mips4/invalid-mips64r2-xfail.s Normal file
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@ -0,0 +1,27 @@
# Instructions that are supposed to be invalid but currently aren't
# This test will XPASS if any insn stops assembling.
#
# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 \
# RUN: 2> %t1
# RUN: not FileCheck %s < %t1
# XFAIL: *
# CHECK-NOT: error
.set noat
deret
di $s8
ei $t6
luxc1 $f19,$s6($s5)
madd $s6,$t5
madd $zero,$t1
maddu $s3,$gp
maddu $t8,$s2
mfc0 $a2,$14,1
mfhc1 $s8,$f24
msub $s7,$k1
msubu $t7,$a1
mtc0 $t1,$29,3
mthc1 $zero,$f16
mul $s0,$s4,$at
rdhwr $sp,$11
suxc1 $f12,$k1($t5)

22
test/MC/Mips/mips4/invalid-mips64r2.s Normal file
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@ -0,0 +1,22 @@
# Instructions that are invalid
#
# FIXME: This test should be moved to the mips5 directory when mips5 is supported
# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 \
# RUN: 2>%t1
# RUN: FileCheck %s < %t1
.set noat
clo $t3,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dsbh $v1,$t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
pause # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
seb $t9,$t7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
seh $v1,$t4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
wsbh $k1,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

15
test/MC/Mips/mips64/invalid-mips64r2-xfail.s Normal file
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@ -0,0 +1,15 @@
# Instructions that are supposed to be invalid but currently aren't
# This test will XPASS if any insn stops assembling.
#
# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 \
# RUN: 2> %t1
# RUN: not FileCheck %s < %t1
# XFAIL: *
# CHECK-NOT: error
.set noat
di $s8
ei $t6
mfhc1 $s8,$f24
mthc1 $zero,$f16
rdhwr $sp,$11

11
test/MC/Mips/mips64/invalid-mips64r2.s
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@ -5,4 +5,13 @@
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
.set noat .set noat
pause # CHECK: requires a CPU feature not currently enabled dsbh $v1,$t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
pause # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
seb $t9,$t7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
seh $v1,$t4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
wsbh $k1,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

1
test/MC/Mips/mips64r2/valid.s
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@ -118,6 +118,7 @@
msub $s7,$k1 msub $s7,$k1
msub.s $f12,$f19,$f10,$f16 msub.s $f12,$f19,$f10,$f16
msubu $t7,$a1 msubu $t7,$a1
mtc0 $t1,$29,3
mtc1 $s8,$f9 mtc1 $s8,$f9
mthc1 $zero,$f16 mthc1 $zero,$f16
mthi $s1 mthi $s1