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First step towards V9 instructions in the V8 backend, two conditional move

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patterns.  This allows emission of this code:

t1:
        save -96, %o6, %o6
        subcc %i0, %i1, %l0
        move %icc, %i0, %i2
        or %g0, %i2, %i0
        restore %g0, %g0, %g0
        retl
        nop

instead of this:

t1:
        save -96, %o6, %o6
        subcc %i0, %i1, %l0
        be .LBBt1_2     !
        nop
.LBBt1_1:       !
        or %g0, %i2, %i0
.LBBt1_2:       !
        restore %g0, %g0, %g0
        retl
        nop

for this:

int %t1(int %a, int %b, int %c) {
        %tmp.2 = seteq int %a, %b
        %tmp3 = select bool %tmp.2, int %a, int %c
        ret int %tmp3
}


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25809 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2006-01-30 05:35:57 +00:00
parent 6f63001214
commit 76afdc9a80
6 changed files with 88 additions and 14 deletions
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8
lib/Target/Sparc/SparcISelDAGToDAG.cpp
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@@ -850,9 +850,15 @@ SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
namespace {
class SparcV8DAGToDAGISel : public SelectionDAGISel {
SparcV8TargetLowering V8Lowering;
/// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
/// make the right decision when generating code for different targets.
const SparcV8Subtarget &Subtarget;
public:
SparcV8DAGToDAGISel(TargetMachine &TM)
: SelectionDAGISel(V8Lowering), V8Lowering(TM) {}
: SelectionDAGISel(V8Lowering), V8Lowering(TM),
Subtarget(TM.getSubtarget<SparcV8Subtarget>()) {
}
SDOperand Select(SDOperand Op);