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Explicitly specify 0b00, i.e, zero rotation, as the rotate filed (Inst{11-10})
for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85271 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -459,14 +459,15 @@ multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
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IIC_iUNAr, opc, "\t$dst, $src",
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[(set GPR:$dst, (opnode GPR:$src))]>,
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Requires<[IsARM, HasV6]> {
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let Inst{19-16} = 0b1111;
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}
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let Inst{11-10} = 0b00;
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let Inst{19-16} = 0b1111;
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}
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def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot),
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IIC_iUNAsi, opc, "\t$dst, $src, ror $rot",
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[(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>,
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Requires<[IsARM, HasV6]> {
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let Inst{19-16} = 0b1111;
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}
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let Inst{19-16} = 0b1111;
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}
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}
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/// AI_bin_rrot - A binary operation with two forms: one whose operand is a
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@ -475,7 +476,9 @@ multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
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def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
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IIC_iALUr, opc, "\t$dst, $LHS, $RHS",
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[(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
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Requires<[IsARM, HasV6]>;
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Requires<[IsARM, HasV6]> {
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let Inst{11-10} = 0b00;
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}
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def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
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IIC_iALUsi, opc, "\t$dst, $LHS, $RHS, ror $rot",
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[(set GPR:$dst, (opnode GPR:$LHS,
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