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* Recognize `addi r1, r2, 0' a move instruction

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* List formats of instructions currently recognized as moves


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15242 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2004-07-26 21:29:00 +00:00
parent 1aab327293
commit 774a297c83
1 changed files with 12 additions and 2 deletions
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14
lib/Target/PowerPC/PowerPCInstrInfo.cpp
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@ -26,7 +26,7 @@ bool PowerPCInstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg,
unsigned& destReg) const {
MachineOpCode oc = MI.getOpcode();
if (oc == PPC32::OR) {
if (oc == PPC32::OR) { // or r1, r2, r2
assert(MI.getNumOperands() == 3 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
@ -37,7 +37,17 @@ bool PowerPCInstrInfo::isMoveInstr(const MachineInstr& MI,
destReg = MI.getOperand(0).getReg();
return true;
}
} else if (oc == PPC32::FMR) {
} else if (oc == PPC32::ADDI) { // addi r1, r2, 0
if (MI.getNumOperands() == 3 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
MI.getOperand(2).isImmediate() &&
MI.getOperand(2).getImmedValue() == 0) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
}
} else if (oc == PPC32::FMR) { // fmr r1, r2
assert(MI.getNumOperands() == 2 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&