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[PowerPC] Don't attempt a 64-bit pow2 division on PPC32
In r224033, in moving the signed power-of-2 division expansion into BuildSDIVPow2, I accidentally made it possible to attempt the lowering for a 64-bit division on PPC32. This later asserts. Fixes PR21928. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224758 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -8966,6 +8966,8 @@ PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
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std::vector<SDNode *> *Created) const {
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// fold (sdiv X, pow2)
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EVT VT = N->getValueType(0);
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if (VT == MVT::i64 && !Subtarget.isPPC64())
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return SDValue();
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if ((VT != MVT::i32 && VT != MVT::i64) ||
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!(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
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return SDValue();
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@ -1,4 +1,5 @@
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; RUN: llc -mcpu=ppc64 < %s | FileCheck %s
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; RUN: llc -mtriple=powerpc-unknown-linux-gnu -mcpu=ppc < %s | FileCheck -check-prefix=CHECK-32 %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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@ -25,6 +26,10 @@ entry:
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; CHECK: sradi [[REG1:[0-9]+]], 3, 3
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; CHECK: addze 3, [[REG1]]
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; CHECK: blr
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; CHECK-32-LABEL @foo8
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; CHECK-32-NOT: sradi
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; CHECK-32: blr
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}
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; Function Attrs: nounwind readnone
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@ -52,6 +57,10 @@ entry:
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; CHECK: addze [[REG2:[0-9]+]], [[REG1]]
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; CHECK: neg 3, [[REG2]]
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; CHECK: blr
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; CHECK-32-LABEL @foo8n
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; CHECK-32-NOT: sradi
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; CHECK-32: blr
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}
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attributes #0 = { nounwind readnone }
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