6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-26 07:34:06 +00:00
Code Issues Projects Releases Wiki Activity

Avoid caching the relocation model on the subtarget, this is for

Browse Source 
two reasons:

a) we're already caching the target machine which contains it,
b) which relocation model you get is dependent upon whether or
not you ask before MCCodeGenInfo is constructed on the target
machine, so avoid any latent issues there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213420 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2014-07-18 22:34:20 +00:00
parent fa034b8738
commit 775dd6e2d6
3 changed files with 10 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
lib/Target/Mips/MipsSubtarget.cpp
View File

@ -104,7 +104,7 @@ static std::string computeDataLayout(const MipsSubtarget &ST) {
MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, bool little, const std::string &FS, bool little,
Reloc::Model _RM, MipsTargetMachine *_TM) MipsTargetMachine *_TM)
: MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips32), : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips32),
MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false), MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false),
IsFPXX(false), IsFP64bit(false), UseOddSPReg(true), IsNaN2008bit(false), IsFPXX(false), IsFP64bit(false), UseOddSPReg(true), IsNaN2008bit(false),
@ -113,8 +113,7 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false), HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false), InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
HasMSA(false), RM(_RM), OverrideMode(NoOverride), TM(_TM), HasMSA(false), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT),
TargetTriple(TT),
DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS, TM))), DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS, TM))),
TSInfo(DL), JITInfo(), InstrInfo(MipsInstrInfo::create(*TM)), TSInfo(DL), JITInfo(), InstrInfo(MipsInstrInfo::create(*TM)),
FrameLowering(MipsFrameLowering::create(*TM, *this)), FrameLowering(MipsFrameLowering::create(*TM, *this)),
@ -174,7 +173,7 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
// Set UseSmallSection. // Set UseSmallSection.
// TODO: Investigate the IsLinux check. I suspect it's really checking for // TODO: Investigate the IsLinux check. I suspect it's really checking for
// bare-metal. // bare-metal.
UseSmallSection = !IsLinux && (RM == Reloc::Static); UseSmallSection = !IsLinux && (TM->getRelocationModel() == Reloc::Static);
} }
/// This overrides the PostRAScheduler bit in the SchedModel for any CPU. /// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
@ -294,3 +293,7 @@ bool MipsSubtarget::useConstantIslands() {
DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n"); DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n");
return Mips16ConstantIslands; return Mips16ConstantIslands;
} }
Reloc::Model MipsSubtarget::getRelocationModel() const {
return TM->getRelocationModel();
}

8
lib/Target/Mips/MipsSubtarget.h
View File

@ -135,9 +135,6 @@ protected:
InstrItineraryData InstrItins; InstrItineraryData InstrItins;
// Relocation Model
Reloc::Model RM;
// We can override the determination of whether we are in mips16 mode // We can override the determination of whether we are in mips16 mode
// as from the command line // as from the command line
enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode; enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
@ -176,8 +173,7 @@ public:
/// This constructor initializes the data members to match that /// This constructor initializes the data members to match that
/// of the specified triple. /// of the specified triple.
MipsSubtarget(const std::string &TT, const std::string &CPU, MipsSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, bool little, Reloc::Model RM, const std::string &FS, bool little, MipsTargetMachine *TM);
MipsTargetMachine *TM);
/// ParseSubtargetFeatures - Parses features string setting specified /// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen. /// subtarget options. Definition of function is auto generated by tblgen.
@ -276,7 +272,7 @@ public:
unsigned stackAlignment() const { return hasMips64() ? 16 : 8; } unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
// Grab relocation model // Grab relocation model
Reloc::Model getRelocationModel() const {return RM;} Reloc::Model getRelocationModel() const;
/// \brief Reset the subtarget for the Mips target. /// \brief Reset the subtarget for the Mips target.
void resetSubtarget(MachineFunction *MF); void resetSubtarget(MachineFunction *MF);

2
lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -56,7 +56,7 @@ MipsTargetMachine::MipsTargetMachine(const Target &T, StringRef TT,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool isLittle) CodeGenOpt::Level OL, bool isLittle)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
Subtarget(TT, CPU, FS, isLittle, RM, this) { Subtarget(TT, CPU, FS, isLittle, this) {
initAsmInfo(); initAsmInfo();
} }