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[mips] Set instruction itineraries of loads, stores and conditional moves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190219 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
0b3d39235a
commit
77e1ebd18f
@ -135,16 +135,16 @@ def SD : Store<"sd", GPR64Opnd, store, IIStore>, LW_FM<0x3f>;
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/// load/store left/right
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let isCodeGenOnly = 1 in {
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def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd>, LW_FM<0x22>;
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def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd>, LW_FM<0x26>;
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def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd>, LW_FM<0x2a>;
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def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd>, LW_FM<0x2e>;
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def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, IILoad>, LW_FM<0x22>;
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def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, IILoad>, LW_FM<0x26>;
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def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, IIStore>, LW_FM<0x2a>;
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def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, IIStore>, LW_FM<0x2e>;
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}
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def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd>, LW_FM<0x1a>;
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def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd>, LW_FM<0x1b>;
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def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd>, LW_FM<0x2c>;
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def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd>, LW_FM<0x2d>;
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def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, IILoad>, LW_FM<0x1a>;
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def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, IILoad>, LW_FM<0x1b>;
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def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, IIStore>, LW_FM<0x2c>;
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def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, IIStore>, LW_FM<0x2d>;
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/// Load-linked, Store-conditional
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def LLD : LLBase<"lld", GPR64Opnd>, LW_FM<0x34>;
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@ -103,28 +103,28 @@ multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
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}
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// Instantiation of instructions.
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def MOVZ_I_I : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, NoItinerary>,
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def MOVZ_I_I : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, IIArith>,
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ADD_FM<0, 0xa>;
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let Predicates = [HasStdEnc], isCodeGenOnly = 1 in {
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def MOVZ_I_I64 : CMov_I_I_FT<"movz", GPR32Opnd, GPR64Opnd,
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NoItinerary>, ADD_FM<0, 0xa>;
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def MOVZ_I64_I : CMov_I_I_FT<"movz", GPR64Opnd, GPR32Opnd,
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NoItinerary>, ADD_FM<0, 0xa>;
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def MOVZ_I64_I64 : CMov_I_I_FT<"movz", GPR64Opnd, GPR64Opnd,
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NoItinerary>, ADD_FM<0, 0xa>;
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def MOVZ_I_I64 : CMov_I_I_FT<"movz", GPR32Opnd, GPR64Opnd, IIArith>,
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ADD_FM<0, 0xa>;
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def MOVZ_I64_I : CMov_I_I_FT<"movz", GPR64Opnd, GPR32Opnd, IIArith>,
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ADD_FM<0, 0xa>;
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def MOVZ_I64_I64 : CMov_I_I_FT<"movz", GPR64Opnd, GPR64Opnd, IIArith>,
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ADD_FM<0, 0xa>;
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}
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def MOVN_I_I : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
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NoItinerary>, ADD_FM<0, 0xb>;
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def MOVN_I_I : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd, IIArith>,
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ADD_FM<0, 0xb>;
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let Predicates = [HasStdEnc], isCodeGenOnly = 1 in {
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def MOVN_I_I64 : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd,
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NoItinerary>, ADD_FM<0, 0xb>;
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def MOVN_I64_I : CMov_I_I_FT<"movn", GPR64Opnd, GPR32Opnd,
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NoItinerary>, ADD_FM<0, 0xb>;
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def MOVN_I64_I64 : CMov_I_I_FT<"movn", GPR64Opnd, GPR64Opnd,
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NoItinerary>, ADD_FM<0, 0xb>;
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def MOVN_I_I64 : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd, IIArith>,
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ADD_FM<0, 0xb>;
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def MOVN_I64_I : CMov_I_I_FT<"movn", GPR64Opnd, GPR32Opnd, IIArith>,
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ADD_FM<0, 0xb>;
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def MOVN_I64_I64 : CMov_I_I_FT<"movn", GPR64Opnd, GPR64Opnd, IIArith>,
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ADD_FM<0, 0xb>;
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}
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def MOVZ_I_S : CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, IIFmove>,
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@ -461,7 +461,7 @@ class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
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class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
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InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
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InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
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[(set RO:$rt, (OpNode Addr:$addr))], NoItinerary, FrmI, opstr> {
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[(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
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let DecoderMethod = "DecodeMem";
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let canFoldAsLoad = 1;
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let mayLoad = 1;
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@ -470,24 +470,26 @@ class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
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class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
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InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
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InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
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[(OpNode RO:$rt, Addr:$addr)], NoItinerary, FrmI, opstr> {
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[(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
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let DecoderMethod = "DecodeMem";
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let mayStore = 1;
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}
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// Load/Store Left/Right
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let canFoldAsLoad = 1 in
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class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO> :
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class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
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InstrItinClass Itin> :
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InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
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!strconcat(opstr, "\t$rt, $addr"),
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[(set RO:$rt, (OpNode addr:$addr, RO:$src))], NoItinerary, FrmI> {
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[(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
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let DecoderMethod = "DecodeMem";
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string Constraints = "$src = $rt";
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}
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class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO> :
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class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
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InstrItinClass Itin> :
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InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
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[(OpNode RO:$rt, addr:$addr)], NoItinerary, FrmI> {
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[(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
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let DecoderMethod = "DecodeMem";
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}
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@ -925,10 +927,10 @@ def SH : Store<"sh", GPR32Opnd, truncstorei16, IIStore>, MMRel, LW_FM<0x29>;
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def SW : Store<"sw", GPR32Opnd, store, IIStore>, MMRel, LW_FM<0x2b>;
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/// load/store left/right
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def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd>, LW_FM<0x22>;
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def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd>, LW_FM<0x26>;
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def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd>, LW_FM<0x2a>;
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def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd>, LW_FM<0x2e>;
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def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, IILoad>, LW_FM<0x22>;
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def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, IILoad>, LW_FM<0x26>;
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def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, IIStore>, LW_FM<0x2a>;
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def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, IIStore>, LW_FM<0x2e>;
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def SYNC : SYNC_FT, SYNC_FM;
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def TEQ : TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
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@ -10,22 +10,23 @@
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define void @f1() nounwind {
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entry:
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; CHECK: lw $[[R1:[0-9]+]], %got(f1.s1)
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; CHECK: addiu $[[R0:[0-9]+]], $[[R1]], %lo(f1.s1)
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; CHECK: lw $[[R7:[0-9]+]], 12($[[R0]])
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; CHECK: lw $[[R3:[0-9]+]], 16($[[R0]])
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; CHECK: lw $[[R4:[0-9]+]], 20($[[R0]])
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; CHECK: lw $[[R5:[0-9]+]], 24($[[R0]])
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; CHECK: lw $[[R6:[0-9]+]], 28($[[R0]])
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; CHECK: sw $[[R6]], 36($sp)
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; CHECK: sw $[[R5]], 32($sp)
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; CHECK: sw $[[R4]], 28($sp)
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; CHECK: sw $[[R3]], 24($sp)
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; CHECK: sw $[[R7]], 20($sp)
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; CHECK: lw $[[R2:[0-9]+]], 8($[[R0]])
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; CHECK: sw $[[R2]], 16($sp)
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; CHECK: lw $6, %lo(f1.s1)($[[R1]])
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; CHECK: lw $7, 4($[[R0]])
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; CHECK-LABEL: f1:
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; CHECK-DAG: lw $[[R1:[0-9]+]], %got(f1.s1)
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; CHECK-DAG: addiu $[[R0:[0-9]+]], $[[R1]], %lo(f1.s1)
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; CHECK-DAG: lw $[[R7:[0-9]+]], 12($[[R0]])
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; CHECK-DAG: lw $[[R3:[0-9]+]], 16($[[R0]])
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; CHECK-DAG: lw $[[R4:[0-9]+]], 20($[[R0]])
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; CHECK-DAG: lw $[[R5:[0-9]+]], 24($[[R0]])
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; CHECK-DAG: lw $[[R6:[0-9]+]], 28($[[R0]])
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; CHECK-DAG: sw $[[R6]], 36($sp)
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; CHECK-DAG: sw $[[R5]], 32($sp)
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; CHECK-DAG: sw $[[R4]], 28($sp)
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; CHECK-DAG: sw $[[R3]], 24($sp)
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; CHECK-DAG: sw $[[R7]], 20($sp)
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; CHECK-DAG: lw $[[R2:[0-9]+]], 8($[[R0]])
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; CHECK-DAG: sw $[[R2]], 16($sp)
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; CHECK-DAG: lw $6, %lo(f1.s1)($[[R1]])
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; CHECK-DAG: lw $7, 4($[[R0]])
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%agg.tmp10 = alloca %struct.S3, align 4
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call void @callee1(float 2.000000e+01, %struct.S1* byval bitcast (%0* @f1.s1 to %struct.S1*)) nounwind
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call void @callee2(%struct.S2* byval @f1.s2) nounwind
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@ -14,10 +14,10 @@ entry:
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; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_LO16
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; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_GOT_HI16
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; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_GOT_LO16
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; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_GOT
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; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_LO16
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; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_CALL_HI16
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; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_CALL_LO16
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; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_GOT
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; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_LO16
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; CHECK: ]
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%0 = load i32* @ext_1, align 4
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