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Drop the W postfix on the 16-bit registers.
This ensures the inline assembly register constraints are properly recognised in TargetLowering::getRegForInlineAsmConstraint. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217479 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Job Noorman
parent
7d822f839f
commit
77f923cfc1
@ -39,7 +39,7 @@ static MCInstrInfo *createMSP430MCInstrInfo() {
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static MCRegisterInfo *createMSP430MCRegisterInfo(StringRef TT) {
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MCRegisterInfo *X = new MCRegisterInfo();
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InitMSP430MCRegisterInfo(X, MSP430::PCW);
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InitMSP430MCRegisterInfo(X, MSP430::PC);
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return X;
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}
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@ -17,7 +17,7 @@ def RetCC_MSP430 : CallingConv<[
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CCIfType<[i8], CCAssignToReg<[R15B, R14B, R13B, R12B]>>,
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// i16 are returned in registers R15, R14, R13, R12
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CCIfType<[i16], CCAssignToReg<[R15W, R14W, R13W, R12W]>>
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CCIfType<[i16], CCAssignToReg<[R15, R14, R13, R12]>>
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]>;
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//===----------------------------------------------------------------------===//
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@ -63,18 +63,18 @@ void MSP430FrameLowering::emitPrologue(MachineFunction &MF) const {
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// Update the frame offset adjustment.
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MFI->setOffsetAdjustment(-NumBytes);
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// Save FPW into the appropriate stack slot...
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// Save FP into the appropriate stack slot...
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BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
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.addReg(MSP430::FPW, RegState::Kill);
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.addReg(MSP430::FP, RegState::Kill);
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// Update FPW with the new base value...
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BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW)
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.addReg(MSP430::SPW);
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// Update FP with the new base value...
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BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FP)
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.addReg(MSP430::SP);
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// Mark the FramePtr as live-in in every block except the entry.
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for (MachineFunction::iterator I = std::next(MF.begin()), E = MF.end();
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I != E; ++I)
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I->addLiveIn(MSP430::FPW);
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I->addLiveIn(MSP430::FP);
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} else
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NumBytes = StackSize - MSP430FI->getCalleeSavedFrameSize();
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@ -86,18 +86,18 @@ void MSP430FrameLowering::emitPrologue(MachineFunction &MF) const {
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if (MBBI != MBB.end())
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DL = MBBI->getDebugLoc();
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if (NumBytes) { // adjust stack pointer: SPW -= numbytes
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// If there is an SUB16ri of SPW immediately before this instruction, merge
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if (NumBytes) { // adjust stack pointer: SP -= numbytes
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// If there is an SUB16ri of SP immediately before this instruction, merge
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// the two.
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//NumBytes -= mergeSPUpdates(MBB, MBBI, true);
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// If there is an ADD16ri or SUB16ri of SPW immediately after this
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// If there is an ADD16ri or SUB16ri of SP immediately after this
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// instruction, merge the two instructions.
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// mergeSPUpdatesDown(MBB, MBBI, &NumBytes);
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if (NumBytes) {
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MachineInstr *MI =
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BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SPW)
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.addReg(MSP430::SPW).addImm(NumBytes);
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BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SP)
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.addReg(MSP430::SP).addImm(NumBytes);
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// The SRW implicit def is dead.
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MI->getOperand(3).setIsDead();
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}
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@ -132,8 +132,8 @@ void MSP430FrameLowering::emitEpilogue(MachineFunction &MF,
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uint64_t FrameSize = StackSize - 2;
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NumBytes = FrameSize - CSSize;
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// pop FPW.
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BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FPW);
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// pop FP.
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BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FP);
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} else
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NumBytes = StackSize - CSSize;
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@ -148,28 +148,28 @@ void MSP430FrameLowering::emitEpilogue(MachineFunction &MF,
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DL = MBBI->getDebugLoc();
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// If there is an ADD16ri or SUB16ri of SPW immediately before this
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// If there is an ADD16ri or SUB16ri of SP immediately before this
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// instruction, merge the two instructions.
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//if (NumBytes || MFI->hasVarSizedObjects())
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// mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
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if (MFI->hasVarSizedObjects()) {
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BuildMI(MBB, MBBI, DL,
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TII.get(MSP430::MOV16rr), MSP430::SPW).addReg(MSP430::FPW);
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TII.get(MSP430::MOV16rr), MSP430::SP).addReg(MSP430::FP);
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if (CSSize) {
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MachineInstr *MI =
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BuildMI(MBB, MBBI, DL,
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TII.get(MSP430::SUB16ri), MSP430::SPW)
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.addReg(MSP430::SPW).addImm(CSSize);
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TII.get(MSP430::SUB16ri), MSP430::SP)
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.addReg(MSP430::SP).addImm(CSSize);
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// The SRW implicit def is dead.
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MI->getOperand(3).setIsDead();
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}
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} else {
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// adjust stack pointer back: SPW += numbytes
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// adjust stack pointer back: SP += numbytes
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if (NumBytes) {
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MachineInstr *MI =
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BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SPW)
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.addReg(MSP430::SPW).addImm(NumBytes);
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BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SP)
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.addReg(MSP430::SP).addImm(NumBytes);
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// The SRW implicit def is dead.
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MI->getOperand(3).setIsDead();
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}
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@ -232,8 +232,8 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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if (!hasReservedCallFrame(MF)) {
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// If the stack pointer can be changed after prologue, turn the
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// adjcallstackup instruction into a 'sub SPW, <amt>' and the
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// adjcallstackdown instruction into 'add SPW, <amt>'
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// adjcallstackup instruction into a 'sub SP, <amt>' and the
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// adjcallstackdown instruction into 'add SP, <amt>'
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// TODO: consider using push / pop instead of sub + store / add
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MachineInstr *Old = I;
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uint64_t Amount = Old->getOperand(0).getImm();
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@ -246,8 +246,8 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineInstr *New = nullptr;
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if (Old->getOpcode() == TII.getCallFrameSetupOpcode()) {
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New = BuildMI(MF, Old->getDebugLoc(),
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TII.get(MSP430::SUB16ri), MSP430::SPW)
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.addReg(MSP430::SPW).addImm(Amount);
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TII.get(MSP430::SUB16ri), MSP430::SP)
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.addReg(MSP430::SP).addImm(Amount);
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} else {
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assert(Old->getOpcode() == TII.getCallFrameDestroyOpcode());
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// factor out the amount the callee already popped.
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@ -255,8 +255,8 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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Amount -= CalleeAmt;
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if (Amount)
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New = BuildMI(MF, Old->getDebugLoc(),
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TII.get(MSP430::ADD16ri), MSP430::SPW)
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.addReg(MSP430::SPW).addImm(Amount);
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TII.get(MSP430::ADD16ri), MSP430::SP)
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.addReg(MSP430::SP).addImm(Amount);
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}
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if (New) {
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@ -274,7 +274,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineInstr *Old = I;
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MachineInstr *New =
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BuildMI(MF, Old->getDebugLoc(), TII.get(MSP430::SUB16ri),
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MSP430::SPW).addReg(MSP430::SPW).addImm(CalleeAmt);
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MSP430::SP).addReg(MSP430::SP).addImm(CalleeAmt);
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// The SRW implicit def is dead.
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New->getOperand(3).setIsDead();
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@ -288,11 +288,11 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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void
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MSP430FrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
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RegScavenger *) const {
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// Create a frame entry for the FPW register that must be saved.
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// Create a frame entry for the FP register that must be saved.
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if (hasFP(MF)) {
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(2, -4, true);
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(void)FrameIdx;
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assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
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"Slot for FPW register must be last in order to be found!");
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"Slot for FP register must be last in order to be found!");
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}
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}
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@ -72,7 +72,7 @@ MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM)
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// Division is expensive
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setIntDivIsCheap(false);
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setStackPointerRegisterToSaveRestore(MSP430::SPW);
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setStackPointerRegisterToSaveRestore(MSP430::SP);
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setBooleanContents(ZeroOrOneBooleanContent);
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setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
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@ -282,7 +282,7 @@ static void AnalyzeArguments(CCState &State,
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SmallVectorImpl<CCValAssign> &ArgLocs,
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const SmallVectorImpl<ArgT> &Args) {
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static const MCPhysReg RegList[] = {
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MSP430::R15W, MSP430::R14W, MSP430::R13W, MSP430::R12W
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MSP430::R15, MSP430::R14, MSP430::R13, MSP430::R12
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};
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static const unsigned NbRegs = array_lengthof(RegList);
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@ -627,7 +627,7 @@ MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
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assert(VA.isMemLoc());
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if (!StackPtr.getNode())
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StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
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StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SP, getPointerTy());
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SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
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StackPtr,
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@ -941,31 +941,31 @@ SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
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Convert = false;
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break;
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case MSP430CC::COND_HS:
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// Res = SRW & 1, no processing is required
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// Res = SR & 1, no processing is required
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break;
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case MSP430CC::COND_LO:
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// Res = ~(SRW & 1)
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// Res = ~(SR & 1)
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Invert = true;
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break;
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case MSP430CC::COND_NE:
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if (andCC) {
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// C = ~Z, thus Res = SRW & 1, no processing is required
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// C = ~Z, thus Res = SR & 1, no processing is required
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} else {
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// Res = ~((SRW >> 1) & 1)
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// Res = ~((SR >> 1) & 1)
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Shift = true;
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Invert = true;
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}
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break;
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case MSP430CC::COND_E:
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Shift = true;
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// C = ~Z for AND instruction, thus we can put Res = ~(SRW & 1), however,
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// Res = (SRW >> 1) & 1 is 1 word shorter.
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// C = ~Z for AND instruction, thus we can put Res = ~(SR & 1), however,
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// Res = (SR >> 1) & 1 is 1 word shorter.
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break;
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}
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EVT VT = Op.getValueType();
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SDValue One = DAG.getConstant(1, VT);
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if (Convert) {
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SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SRW,
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SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SR,
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MVT::i16, Flag);
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if (Shift)
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// FIXME: somewhere this is turned into a SRL, lower it MSP specific?
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@ -1074,7 +1074,7 @@ SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op,
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SDLoc dl(Op); // FIXME probably not meaningful
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unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
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SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
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MSP430::FPW, VT);
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MSP430::FP, VT);
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while (Depth--)
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FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
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MachinePointerInfo(),
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@ -111,8 +111,8 @@ def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
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// a stack adjustment and the codegen must know that they may modify the stack
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// pointer before prolog-epilog rewriting occurs.
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// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
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// sub / add which can clobber SRW.
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let Defs = [SPW, SRW], Uses = [SPW] in {
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// sub / add which can clobber SR.
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let Defs = [SP, SR], Uses = [SP] in {
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def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt),
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"#ADJCALLSTACKDOWN",
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[(MSP430callseq_start timm:$amt)]>;
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@ -130,7 +130,7 @@ let usesCustomInserter = 1 in {
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"# Select16 PSEUDO",
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[(set GR16:$dst,
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(MSP430selectcc GR16:$src, GR16:$src2, imm:$cc))]>;
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let Defs = [SRW] in {
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let Defs = [SR] in {
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def Shl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
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"# Shl8 PSEUDO",
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[(set GR8:$dst, (MSP430shl GR8:$src, GR8:$cnt))]>;
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@ -192,7 +192,7 @@ let isBarrier = 1 in {
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}
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// Conditional branches
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let Uses = [SRW] in
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let Uses = [SR] in
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def JCC : CJForm<0, 0,
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(outs), (ins jmptarget:$dst, cc:$cc),
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"j$cc\t$dst",
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@ -207,8 +207,8 @@ let isCall = 1 in
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// a use to prevent stack-pointer assignments that appear immediately
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// before calls from potentially appearing dead. Uses for argument
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// registers are added manually.
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let Defs = [R12W, R13W, R14W, R15W, SRW],
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Uses = [SPW] in {
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let Defs = [R12, R13, R14, R15, SR],
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Uses = [SP] in {
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def CALLi : II16i<0x0,
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(outs), (ins i16imm:$dst),
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"call\t$dst", [(MSP430call imm:$dst)]>;
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@ -224,7 +224,7 @@ let isCall = 1 in
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//===----------------------------------------------------------------------===//
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// Miscellaneous Instructions...
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//
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let Defs = [SPW], Uses = [SPW], neverHasSideEffects=1 in {
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let Defs = [SP], Uses = [SP], neverHasSideEffects=1 in {
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let mayLoad = 1 in
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def POP16r : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes,
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(outs GR16:$reg), (ins), "pop.w\t$reg", []>;
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@ -337,7 +337,7 @@ def MOV16mm : I16mm<0x0,
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let Constraints = "$src = $dst" in {
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let Defs = [SRW] in {
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let Defs = [SR] in {
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let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
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@ -345,24 +345,24 @@ def ADD8rr : I8rr<0x0,
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(outs GR8:$dst), (ins GR8:$src, GR8:$src2),
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"add.b\t{$src2, $dst}",
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[(set GR8:$dst, (add GR8:$src, GR8:$src2)),
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(implicit SRW)]>;
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(implicit SR)]>;
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def ADD16rr : I16rr<0x0,
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(outs GR16:$dst), (ins GR16:$src, GR16:$src2),
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"add.w\t{$src2, $dst}",
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[(set GR16:$dst, (add GR16:$src, GR16:$src2)),
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(implicit SRW)]>;
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(implicit SR)]>;
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}
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def ADD8rm : I8rm<0x0,
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(outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
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"add.b\t{$src2, $dst}",
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[(set GR8:$dst, (add GR8:$src, (load addr:$src2))),
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(implicit SRW)]>;
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(implicit SR)]>;
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def ADD16rm : I16rm<0x0,
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(outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
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"add.w\t{$src2, $dst}",
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[(set GR16:$dst, (add GR16:$src, (load addr:$src2))),
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(implicit SRW)]>;
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(implicit SR)]>;
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let mayLoad = 1, hasExtraDefRegAllocReq = 1,
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Constraints = "$base = $base_wb, $src = $dst" in {
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@ -381,160 +381,160 @@ def ADD8ri : I8ri<0x0,
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(outs GR8:$dst), (ins GR8:$src, i8imm:$src2),
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"add.b\t{$src2, $dst}",
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[(set GR8:$dst, (add GR8:$src, imm:$src2)),
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(implicit SRW)]>;
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(implicit SR)]>;
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def ADD16ri : I16ri<0x0,
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(outs GR16:$dst), (ins GR16:$src, i16imm:$src2),
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"add.w\t{$src2, $dst}",
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[(set GR16:$dst, (add GR16:$src, imm:$src2)),
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(implicit SRW)]>;
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(implicit SR)]>;
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let Constraints = "" in {
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def ADD8mr : I8mr<0x0,
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(outs), (ins memdst:$dst, GR8:$src),
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"add.b\t{$src, $dst}",
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[(store (add (load addr:$dst), GR8:$src), addr:$dst),
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(implicit SRW)]>;
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(implicit SR)]>;
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def ADD16mr : I16mr<0x0,
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(outs), (ins memdst:$dst, GR16:$src),
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"add.w\t{$src, $dst}",
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[(store (add (load addr:$dst), GR16:$src), addr:$dst),
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(implicit SRW)]>;
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(implicit SR)]>;
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def ADD8mi : I8mi<0x0,
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(outs), (ins memdst:$dst, i8imm:$src),
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"add.b\t{$src, $dst}",
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[(store (add (load addr:$dst), (i8 imm:$src)), addr:$dst),
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(implicit SRW)]>;
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(implicit SR)]>;
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def ADD16mi : I16mi<0x0,
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(outs), (ins memdst:$dst, i16imm:$src),
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"add.w\t{$src, $dst}",
|
||||
[(store (add (load addr:$dst), (i16 imm:$src)), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
def ADD8mm : I8mm<0x0,
|
||||
(outs), (ins memdst:$dst, memsrc:$src),
|
||||
"add.b\t{$src, $dst}",
|
||||
[(store (add (load addr:$dst),
|
||||
(i8 (load addr:$src))), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def ADD16mm : I16mm<0x0,
|
||||
(outs), (ins memdst:$dst, memsrc:$src),
|
||||
"add.w\t{$src, $dst}",
|
||||
[(store (add (load addr:$dst),
|
||||
(i16 (load addr:$src))), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
}
|
||||
|
||||
let Uses = [SRW] in {
|
||||
let Uses = [SR] in {
|
||||
|
||||
let isCommutable = 1 in { // X = ADDC Y, Z == X = ADDC Z, Y
|
||||
def ADC8rr : I8rr<0x0,
|
||||
(outs GR8:$dst), (ins GR8:$src, GR8:$src2),
|
||||
"addc.b\t{$src2, $dst}",
|
||||
[(set GR8:$dst, (adde GR8:$src, GR8:$src2)),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def ADC16rr : I16rr<0x0,
|
||||
(outs GR16:$dst), (ins GR16:$src, GR16:$src2),
|
||||
"addc.w\t{$src2, $dst}",
|
||||
[(set GR16:$dst, (adde GR16:$src, GR16:$src2)),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
} // isCommutable
|
||||
|
||||
def ADC8ri : I8ri<0x0,
|
||||
(outs GR8:$dst), (ins GR8:$src, i8imm:$src2),
|
||||
"addc.b\t{$src2, $dst}",
|
||||
[(set GR8:$dst, (adde GR8:$src, imm:$src2)),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def ADC16ri : I16ri<0x0,
|
||||
(outs GR16:$dst), (ins GR16:$src, i16imm:$src2),
|
||||
"addc.w\t{$src2, $dst}",
|
||||
[(set GR16:$dst, (adde GR16:$src, imm:$src2)),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
def ADC8rm : I8rm<0x0,
|
||||
(outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
|
||||
"addc.b\t{$src2, $dst}",
|
||||
[(set GR8:$dst, (adde GR8:$src, (load addr:$src2))),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def ADC16rm : I16rm<0x0,
|
||||
(outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
|
||||
"addc.w\t{$src2, $dst}",
|
||||
[(set GR16:$dst, (adde GR16:$src, (load addr:$src2))),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
let Constraints = "" in {
|
||||
def ADC8mr : I8mr<0x0,
|
||||
(outs), (ins memdst:$dst, GR8:$src),
|
||||
"addc.b\t{$src, $dst}",
|
||||
[(store (adde (load addr:$dst), GR8:$src), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def ADC16mr : I16mr<0x0,
|
||||
(outs), (ins memdst:$dst, GR16:$src),
|
||||
"addc.w\t{$src, $dst}",
|
||||
[(store (adde (load addr:$dst), GR16:$src), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
def ADC8mi : I8mi<0x0,
|
||||
(outs), (ins memdst:$dst, i8imm:$src),
|
||||
"addc.b\t{$src, $dst}",
|
||||
[(store (adde (load addr:$dst), (i8 imm:$src)), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def ADC16mi : I16mi<0x0,
|
||||
(outs), (ins memdst:$dst, i16imm:$src),
|
||||
"addc.w\t{$src, $dst}",
|
||||
[(store (adde (load addr:$dst), (i16 imm:$src)), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
def ADC8mm : I8mm<0x0,
|
||||
(outs), (ins memdst:$dst, memsrc:$src),
|
||||
"addc.b\t{$src, $dst}",
|
||||
[(store (adde (load addr:$dst),
|
||||
(i8 (load addr:$src))), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def ADC16mm : I8mm<0x0,
|
||||
(outs), (ins memdst:$dst, memsrc:$src),
|
||||
"addc.w\t{$src, $dst}",
|
||||
[(store (adde (load addr:$dst),
|
||||
(i16 (load addr:$src))), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
}
|
||||
|
||||
} // Uses = [SRW]
|
||||
} // Uses = [SR]
|
||||
|
||||
let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
|
||||
def AND8rr : I8rr<0x0,
|
||||
(outs GR8:$dst), (ins GR8:$src, GR8:$src2),
|
||||
"and.b\t{$src2, $dst}",
|
||||
[(set GR8:$dst, (and GR8:$src, GR8:$src2)),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def AND16rr : I16rr<0x0,
|
||||
(outs GR16:$dst), (ins GR16:$src, GR16:$src2),
|
||||
"and.w\t{$src2, $dst}",
|
||||
[(set GR16:$dst, (and GR16:$src, GR16:$src2)),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
}
|
||||
|
||||
def AND8ri : I8ri<0x0,
|
||||
(outs GR8:$dst), (ins GR8:$src, i8imm:$src2),
|
||||
"and.b\t{$src2, $dst}",
|
||||
[(set GR8:$dst, (and GR8:$src, imm:$src2)),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def AND16ri : I16ri<0x0,
|
||||
(outs GR16:$dst), (ins GR16:$src, i16imm:$src2),
|
||||
"and.w\t{$src2, $dst}",
|
||||
[(set GR16:$dst, (and GR16:$src, imm:$src2)),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
def AND8rm : I8rm<0x0,
|
||||
(outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
|
||||
"and.b\t{$src2, $dst}",
|
||||
[(set GR8:$dst, (and GR8:$src, (load addr:$src2))),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def AND16rm : I16rm<0x0,
|
||||
(outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
|
||||
"and.w\t{$src2, $dst}",
|
||||
[(set GR16:$dst, (and GR16:$src, (load addr:$src2))),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
let mayLoad = 1, hasExtraDefRegAllocReq = 1,
|
||||
Constraints = "$base = $base_wb, $src = $dst" in {
|
||||
@ -553,36 +553,36 @@ def AND8mr : I8mr<0x0,
|
||||
(outs), (ins memdst:$dst, GR8:$src),
|
||||
"and.b\t{$src, $dst}",
|
||||
[(store (and (load addr:$dst), GR8:$src), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def AND16mr : I16mr<0x0,
|
||||
(outs), (ins memdst:$dst, GR16:$src),
|
||||
"and.w\t{$src, $dst}",
|
||||
[(store (and (load addr:$dst), GR16:$src), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
def AND8mi : I8mi<0x0,
|
||||
(outs), (ins memdst:$dst, i8imm:$src),
|
||||
"and.b\t{$src, $dst}",
|
||||
[(store (and (load addr:$dst), (i8 imm:$src)), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def AND16mi : I16mi<0x0,
|
||||
(outs), (ins memdst:$dst, i16imm:$src),
|
||||
"and.w\t{$src, $dst}",
|
||||
[(store (and (load addr:$dst), (i16 imm:$src)), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
def AND8mm : I8mm<0x0,
|
||||
(outs), (ins memdst:$dst, memsrc:$src),
|
||||
"and.b\t{$src, $dst}",
|
||||
[(store (and (load addr:$dst),
|
||||
(i8 (load addr:$src))), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def AND16mm : I16mm<0x0,
|
||||
(outs), (ins memdst:$dst, memsrc:$src),
|
||||
"and.w\t{$src, $dst}",
|
||||
[(store (and (load addr:$dst),
|
||||
(i16 (load addr:$src))), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
}
|
||||
|
||||
let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
|
||||
@ -703,35 +703,35 @@ def XOR8rr : I8rr<0x0,
|
||||
(outs GR8:$dst), (ins GR8:$src, GR8:$src2),
|
||||
"xor.b\t{$src2, $dst}",
|
||||
[(set GR8:$dst, (xor GR8:$src, GR8:$src2)),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def XOR16rr : I16rr<0x0,
|
||||
(outs GR16:$dst), (ins GR16:$src, GR16:$src2),
|
||||
"xor.w\t{$src2, $dst}",
|
||||
[(set GR16:$dst, (xor GR16:$src, GR16:$src2)),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
}
|
||||
|
||||
def XOR8ri : I8ri<0x0,
|
||||
(outs GR8:$dst), (ins GR8:$src, i8imm:$src2),
|
||||
"xor.b\t{$src2, $dst}",
|
||||
[(set GR8:$dst, (xor GR8:$src, imm:$src2)),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def XOR16ri : I16ri<0x0,
|
||||
(outs GR16:$dst), (ins GR16:$src, i16imm:$src2),
|
||||
"xor.w\t{$src2, $dst}",
|
||||
[(set GR16:$dst, (xor GR16:$src, imm:$src2)),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
def XOR8rm : I8rm<0x0,
|
||||
(outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
|
||||
"xor.b\t{$src2, $dst}",
|
||||
[(set GR8:$dst, (xor GR8:$src, (load addr:$src2))),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def XOR16rm : I16rm<0x0,
|
||||
(outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
|
||||
"xor.w\t{$src2, $dst}",
|
||||
[(set GR16:$dst, (xor GR16:$src, (load addr:$src2))),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
let mayLoad = 1, hasExtraDefRegAllocReq = 1,
|
||||
Constraints = "$base = $base_wb, $src = $dst" in {
|
||||
@ -750,34 +750,34 @@ def XOR8mr : I8mr<0x0,
|
||||
(outs), (ins memdst:$dst, GR8:$src),
|
||||
"xor.b\t{$src, $dst}",
|
||||
[(store (xor (load addr:$dst), GR8:$src), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def XOR16mr : I16mr<0x0,
|
||||
(outs), (ins memdst:$dst, GR16:$src),
|
||||
"xor.w\t{$src, $dst}",
|
||||
[(store (xor (load addr:$dst), GR16:$src), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
def XOR8mi : I8mi<0x0,
|
||||
(outs), (ins memdst:$dst, i8imm:$src),
|
||||
"xor.b\t{$src, $dst}",
|
||||
[(store (xor (load addr:$dst), (i8 imm:$src)), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def XOR16mi : I16mi<0x0,
|
||||
(outs), (ins memdst:$dst, i16imm:$src),
|
||||
"xor.w\t{$src, $dst}",
|
||||
[(store (xor (load addr:$dst), (i16 imm:$src)), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
def XOR8mm : I8mm<0x0,
|
||||
(outs), (ins memdst:$dst, memsrc:$src),
|
||||
"xor.b\t{$src, $dst}",
|
||||
[(store (xor (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def XOR16mm : I16mm<0x0,
|
||||
(outs), (ins memdst:$dst, memsrc:$src),
|
||||
"xor.w\t{$src, $dst}",
|
||||
[(store (xor (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
}
|
||||
|
||||
|
||||
@ -785,34 +785,34 @@ def SUB8rr : I8rr<0x0,
|
||||
(outs GR8:$dst), (ins GR8:$src, GR8:$src2),
|
||||
"sub.b\t{$src2, $dst}",
|
||||
[(set GR8:$dst, (sub GR8:$src, GR8:$src2)),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def SUB16rr : I16rr<0x0,
|
||||
(outs GR16:$dst), (ins GR16:$src, GR16:$src2),
|
||||
"sub.w\t{$src2, $dst}",
|
||||
[(set GR16:$dst, (sub GR16:$src, GR16:$src2)),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
def SUB8ri : I8ri<0x0,
|
||||
(outs GR8:$dst), (ins GR8:$src, i8imm:$src2),
|
||||
"sub.b\t{$src2, $dst}",
|
||||
[(set GR8:$dst, (sub GR8:$src, imm:$src2)),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def SUB16ri : I16ri<0x0,
|
||||
(outs GR16:$dst), (ins GR16:$src, i16imm:$src2),
|
||||
"sub.w\t{$src2, $dst}",
|
||||
[(set GR16:$dst, (sub GR16:$src, imm:$src2)),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
def SUB8rm : I8rm<0x0,
|
||||
(outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
|
||||
"sub.b\t{$src2, $dst}",
|
||||
[(set GR8:$dst, (sub GR8:$src, (load addr:$src2))),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def SUB16rm : I16rm<0x0,
|
||||
(outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
|
||||
"sub.w\t{$src2, $dst}",
|
||||
[(set GR16:$dst, (sub GR16:$src, (load addr:$src2))),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
let mayLoad = 1, hasExtraDefRegAllocReq = 1,
|
||||
Constraints = "$base = $base_wb, $src = $dst" in {
|
||||
@ -831,153 +831,153 @@ def SUB8mr : I8mr<0x0,
|
||||
(outs), (ins memdst:$dst, GR8:$src),
|
||||
"sub.b\t{$src, $dst}",
|
||||
[(store (sub (load addr:$dst), GR8:$src), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def SUB16mr : I16mr<0x0,
|
||||
(outs), (ins memdst:$dst, GR16:$src),
|
||||
"sub.w\t{$src, $dst}",
|
||||
[(store (sub (load addr:$dst), GR16:$src), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
def SUB8mi : I8mi<0x0,
|
||||
(outs), (ins memdst:$dst, i8imm:$src),
|
||||
"sub.b\t{$src, $dst}",
|
||||
[(store (sub (load addr:$dst), (i8 imm:$src)), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def SUB16mi : I16mi<0x0,
|
||||
(outs), (ins memdst:$dst, i16imm:$src),
|
||||
"sub.w\t{$src, $dst}",
|
||||
[(store (sub (load addr:$dst), (i16 imm:$src)), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
def SUB8mm : I8mm<0x0,
|
||||
(outs), (ins memdst:$dst, memsrc:$src),
|
||||
"sub.b\t{$src, $dst}",
|
||||
[(store (sub (load addr:$dst),
|
||||
(i8 (load addr:$src))), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def SUB16mm : I16mm<0x0,
|
||||
(outs), (ins memdst:$dst, memsrc:$src),
|
||||
"sub.w\t{$src, $dst}",
|
||||
[(store (sub (load addr:$dst),
|
||||
(i16 (load addr:$src))), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
}
|
||||
|
||||
let Uses = [SRW] in {
|
||||
let Uses = [SR] in {
|
||||
def SBC8rr : I8rr<0x0,
|
||||
(outs GR8:$dst), (ins GR8:$src, GR8:$src2),
|
||||
"subc.b\t{$src2, $dst}",
|
||||
[(set GR8:$dst, (sube GR8:$src, GR8:$src2)),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def SBC16rr : I16rr<0x0,
|
||||
(outs GR16:$dst), (ins GR16:$src, GR16:$src2),
|
||||
"subc.w\t{$src2, $dst}",
|
||||
[(set GR16:$dst, (sube GR16:$src, GR16:$src2)),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
def SBC8ri : I8ri<0x0,
|
||||
(outs GR8:$dst), (ins GR8:$src, i8imm:$src2),
|
||||
"subc.b\t{$src2, $dst}",
|
||||
[(set GR8:$dst, (sube GR8:$src, imm:$src2)),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def SBC16ri : I16ri<0x0,
|
||||
(outs GR16:$dst), (ins GR16:$src, i16imm:$src2),
|
||||
"subc.w\t{$src2, $dst}",
|
||||
[(set GR16:$dst, (sube GR16:$src, imm:$src2)),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
def SBC8rm : I8rm<0x0,
|
||||
(outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
|
||||
"subc.b\t{$src2, $dst}",
|
||||
[(set GR8:$dst, (sube GR8:$src, (load addr:$src2))),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def SBC16rm : I16rm<0x0,
|
||||
(outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
|
||||
"subc.w\t{$src2, $dst}",
|
||||
[(set GR16:$dst, (sube GR16:$src, (load addr:$src2))),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
let Constraints = "" in {
|
||||
def SBC8mr : I8mr<0x0,
|
||||
(outs), (ins memdst:$dst, GR8:$src),
|
||||
"subc.b\t{$src, $dst}",
|
||||
[(store (sube (load addr:$dst), GR8:$src), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def SBC16mr : I16mr<0x0,
|
||||
(outs), (ins memdst:$dst, GR16:$src),
|
||||
"subc.w\t{$src, $dst}",
|
||||
[(store (sube (load addr:$dst), GR16:$src), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
def SBC8mi : I8mi<0x0,
|
||||
(outs), (ins memdst:$dst, i8imm:$src),
|
||||
"subc.b\t{$src, $dst}",
|
||||
[(store (sube (load addr:$dst), (i8 imm:$src)), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def SBC16mi : I16mi<0x0,
|
||||
(outs), (ins memdst:$dst, i16imm:$src),
|
||||
"subc.w\t{$src, $dst}",
|
||||
[(store (sube (load addr:$dst), (i16 imm:$src)), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
def SBC8mm : I8mm<0x0,
|
||||
(outs), (ins memdst:$dst, memsrc:$src),
|
||||
"subc.b\t{$src, $dst}",
|
||||
[(store (sube (load addr:$dst),
|
||||
(i8 (load addr:$src))), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def SBC16mm : I16mm<0x0,
|
||||
(outs), (ins memdst:$dst, memsrc:$src),
|
||||
"subc.w\t{$src, $dst}",
|
||||
[(store (sube (load addr:$dst),
|
||||
(i16 (load addr:$src))), addr:$dst),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
}
|
||||
|
||||
} // Uses = [SRW]
|
||||
} // Uses = [SR]
|
||||
|
||||
// FIXME: memory variant!
|
||||
def SAR8r1 : II8r<0x0,
|
||||
(outs GR8:$dst), (ins GR8:$src),
|
||||
"rra.b\t$dst",
|
||||
[(set GR8:$dst, (MSP430rra GR8:$src)),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def SAR16r1 : II16r<0x0,
|
||||
(outs GR16:$dst), (ins GR16:$src),
|
||||
"rra.w\t$dst",
|
||||
[(set GR16:$dst, (MSP430rra GR16:$src)),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
def SHL8r1 : I8rr<0x0,
|
||||
(outs GR8:$dst), (ins GR8:$src),
|
||||
"rla.b\t$dst",
|
||||
[(set GR8:$dst, (MSP430rla GR8:$src)),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def SHL16r1 : I16rr<0x0,
|
||||
(outs GR16:$dst), (ins GR16:$src),
|
||||
"rla.w\t$dst",
|
||||
[(set GR16:$dst, (MSP430rla GR16:$src)),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
def SAR8r1c : Pseudo<(outs GR8:$dst), (ins GR8:$src),
|
||||
"clrc\n\t"
|
||||
"rrc.b\t$dst",
|
||||
[(set GR8:$dst, (MSP430rrc GR8:$src)),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def SAR16r1c : Pseudo<(outs GR16:$dst), (ins GR16:$src),
|
||||
"clrc\n\t"
|
||||
"rrc.w\t$dst",
|
||||
[(set GR16:$dst, (MSP430rrc GR16:$src)),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
// FIXME: Memory sext's ?
|
||||
def SEXT16r : II16r<0x0,
|
||||
(outs GR16:$dst), (ins GR16:$src),
|
||||
"sxt\t$dst",
|
||||
[(set GR16:$dst, (sext_inreg GR16:$src, i8)),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
} // Defs = [SRW]
|
||||
} // Defs = [SR]
|
||||
|
||||
def ZEXT16r : I8rr<0x0,
|
||||
(outs GR16:$dst), (ins GR16:$src),
|
||||
@ -993,57 +993,57 @@ def SWPB16r : II16r<0x0,
|
||||
} // Constraints = "$src = $dst"
|
||||
|
||||
// Integer comparisons
|
||||
let Defs = [SRW] in {
|
||||
let Defs = [SR] in {
|
||||
def CMP8rr : I8rr<0x0,
|
||||
(outs), (ins GR8:$src, GR8:$src2),
|
||||
"cmp.b\t{$src2, $src}",
|
||||
[(MSP430cmp GR8:$src, GR8:$src2), (implicit SRW)]>;
|
||||
[(MSP430cmp GR8:$src, GR8:$src2), (implicit SR)]>;
|
||||
def CMP16rr : I16rr<0x0,
|
||||
(outs), (ins GR16:$src, GR16:$src2),
|
||||
"cmp.w\t{$src2, $src}",
|
||||
[(MSP430cmp GR16:$src, GR16:$src2), (implicit SRW)]>;
|
||||
[(MSP430cmp GR16:$src, GR16:$src2), (implicit SR)]>;
|
||||
|
||||
def CMP8ri : I8ri<0x0,
|
||||
(outs), (ins GR8:$src, i8imm:$src2),
|
||||
"cmp.b\t{$src2, $src}",
|
||||
[(MSP430cmp GR8:$src, imm:$src2), (implicit SRW)]>;
|
||||
[(MSP430cmp GR8:$src, imm:$src2), (implicit SR)]>;
|
||||
def CMP16ri : I16ri<0x0,
|
||||
(outs), (ins GR16:$src, i16imm:$src2),
|
||||
"cmp.w\t{$src2, $src}",
|
||||
[(MSP430cmp GR16:$src, imm:$src2), (implicit SRW)]>;
|
||||
[(MSP430cmp GR16:$src, imm:$src2), (implicit SR)]>;
|
||||
|
||||
def CMP8mi : I8mi<0x0,
|
||||
(outs), (ins memsrc:$src, i8imm:$src2),
|
||||
"cmp.b\t{$src2, $src}",
|
||||
[(MSP430cmp (load addr:$src),
|
||||
(i8 imm:$src2)), (implicit SRW)]>;
|
||||
(i8 imm:$src2)), (implicit SR)]>;
|
||||
def CMP16mi : I16mi<0x0,
|
||||
(outs), (ins memsrc:$src, i16imm:$src2),
|
||||
"cmp.w\t{$src2, $src}",
|
||||
[(MSP430cmp (load addr:$src),
|
||||
(i16 imm:$src2)), (implicit SRW)]>;
|
||||
(i16 imm:$src2)), (implicit SR)]>;
|
||||
|
||||
def CMP8rm : I8rm<0x0,
|
||||
(outs), (ins GR8:$src, memsrc:$src2),
|
||||
"cmp.b\t{$src2, $src}",
|
||||
[(MSP430cmp GR8:$src, (load addr:$src2)),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def CMP16rm : I16rm<0x0,
|
||||
(outs), (ins GR16:$src, memsrc:$src2),
|
||||
"cmp.w\t{$src2, $src}",
|
||||
[(MSP430cmp GR16:$src, (load addr:$src2)),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
def CMP8mr : I8mr<0x0,
|
||||
(outs), (ins memsrc:$src, GR8:$src2),
|
||||
"cmp.b\t{$src2, $src}",
|
||||
[(MSP430cmp (load addr:$src), GR8:$src2),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def CMP16mr : I16mr<0x0,
|
||||
(outs), (ins memsrc:$src, GR16:$src2),
|
||||
"cmp.w\t{$src2, $src}",
|
||||
[(MSP430cmp (load addr:$src), GR16:$src2),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
|
||||
// BIT TESTS, just sets condition codes
|
||||
@ -1053,56 +1053,56 @@ def BIT8rr : I8rr<0x0,
|
||||
(outs), (ins GR8:$src, GR8:$src2),
|
||||
"bit.b\t{$src2, $src}",
|
||||
[(MSP430cmp (and_su GR8:$src, GR8:$src2), 0),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def BIT16rr : I16rr<0x0,
|
||||
(outs), (ins GR16:$src, GR16:$src2),
|
||||
"bit.w\t{$src2, $src}",
|
||||
[(MSP430cmp (and_su GR16:$src, GR16:$src2), 0),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
}
|
||||
def BIT8ri : I8ri<0x0,
|
||||
(outs), (ins GR8:$src, i8imm:$src2),
|
||||
"bit.b\t{$src2, $src}",
|
||||
[(MSP430cmp (and_su GR8:$src, imm:$src2), 0),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def BIT16ri : I16ri<0x0,
|
||||
(outs), (ins GR16:$src, i16imm:$src2),
|
||||
"bit.w\t{$src2, $src}",
|
||||
[(MSP430cmp (and_su GR16:$src, imm:$src2), 0),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
def BIT8rm : I8rm<0x0,
|
||||
(outs), (ins GR8:$src, memdst:$src2),
|
||||
"bit.b\t{$src2, $src}",
|
||||
[(MSP430cmp (and_su GR8:$src, (load addr:$src2)), 0),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def BIT16rm : I16rm<0x0,
|
||||
(outs), (ins GR16:$src, memdst:$src2),
|
||||
"bit.w\t{$src2, $src}",
|
||||
[(MSP430cmp (and_su GR16:$src, (load addr:$src2)), 0),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
def BIT8mr : I8mr<0x0,
|
||||
(outs), (ins memsrc:$src, GR8:$src2),
|
||||
"bit.b\t{$src2, $src}",
|
||||
[(MSP430cmp (and_su (load addr:$src), GR8:$src2), 0),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def BIT16mr : I16mr<0x0,
|
||||
(outs), (ins memsrc:$src, GR16:$src2),
|
||||
"bit.w\t{$src2, $src}",
|
||||
[(MSP430cmp (and_su (load addr:$src), GR16:$src2), 0),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
def BIT8mi : I8mi<0x0,
|
||||
(outs), (ins memsrc:$src, i8imm:$src2),
|
||||
"bit.b\t{$src2, $src}",
|
||||
[(MSP430cmp (and_su (load addr:$src), (i8 imm:$src2)), 0),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def BIT16mi : I16mi<0x0,
|
||||
(outs), (ins memsrc:$src, i16imm:$src2),
|
||||
"bit.w\t{$src2, $src}",
|
||||
[(MSP430cmp (and_su (load addr:$src), (i16 imm:$src2)), 0),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
|
||||
def BIT8mm : I8mm<0x0,
|
||||
(outs), (ins memsrc:$src, memsrc:$src2),
|
||||
@ -1110,15 +1110,15 @@ def BIT8mm : I8mm<0x0,
|
||||
[(MSP430cmp (and_su (i8 (load addr:$src)),
|
||||
(load addr:$src2)),
|
||||
0),
|
||||
(implicit SRW)]>;
|
||||
(implicit SR)]>;
|
||||
def BIT16mm : I16mm<0x0,
|
||||
(outs), (ins memsrc:$src, memsrc:$src2),
|
||||
"bit.w\t{$src2, $src}",
|
||||
[(MSP430cmp (and_su (i16 (load addr:$src)),
|
||||
(load addr:$src2)),
|
||||
0),
|
||||
(implicit SRW)]>;
|
||||
} // Defs = [SRW]
|
||||
(implicit SR)]>;
|
||||
} // Defs = [SR]
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Non-Instruction Patterns
|
||||
|
||||
@ -33,32 +33,32 @@ using namespace llvm;
|
||||
|
||||
// FIXME: Provide proper call frame setup / destroy opcodes.
|
||||
MSP430RegisterInfo::MSP430RegisterInfo()
|
||||
: MSP430GenRegisterInfo(MSP430::PCW) {}
|
||||
: MSP430GenRegisterInfo(MSP430::PC) {}
|
||||
|
||||
const MCPhysReg*
|
||||
MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
|
||||
const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
|
||||
const Function* F = MF->getFunction();
|
||||
static const MCPhysReg CalleeSavedRegs[] = {
|
||||
MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
|
||||
MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
|
||||
MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7,
|
||||
MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
|
||||
0
|
||||
};
|
||||
static const MCPhysReg CalleeSavedRegsFP[] = {
|
||||
MSP430::R5W, MSP430::R6W, MSP430::R7W,
|
||||
MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
|
||||
MSP430::R5, MSP430::R6, MSP430::R7,
|
||||
MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
|
||||
0
|
||||
};
|
||||
static const MCPhysReg CalleeSavedRegsIntr[] = {
|
||||
MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
|
||||
MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
|
||||
MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W,
|
||||
MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7,
|
||||
MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
|
||||
MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15,
|
||||
0
|
||||
};
|
||||
static const MCPhysReg CalleeSavedRegsIntrFP[] = {
|
||||
MSP430::R5W, MSP430::R6W, MSP430::R7W,
|
||||
MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
|
||||
MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W,
|
||||
MSP430::R5, MSP430::R6, MSP430::R7,
|
||||
MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
|
||||
MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15,
|
||||
0
|
||||
};
|
||||
|
||||
@ -80,15 +80,15 @@ BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
|
||||
Reserved.set(MSP430::SPB);
|
||||
Reserved.set(MSP430::SRB);
|
||||
Reserved.set(MSP430::CGB);
|
||||
Reserved.set(MSP430::PCW);
|
||||
Reserved.set(MSP430::SPW);
|
||||
Reserved.set(MSP430::SRW);
|
||||
Reserved.set(MSP430::CGW);
|
||||
Reserved.set(MSP430::PC);
|
||||
Reserved.set(MSP430::SP);
|
||||
Reserved.set(MSP430::SR);
|
||||
Reserved.set(MSP430::CG);
|
||||
|
||||
// Mark frame pointer as reserved if needed.
|
||||
if (TFI->hasFP(MF)) {
|
||||
Reserved.set(MSP430::FPB);
|
||||
Reserved.set(MSP430::FPW);
|
||||
Reserved.set(MSP430::FP);
|
||||
}
|
||||
|
||||
return Reserved;
|
||||
@ -113,7 +113,7 @@ MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
DebugLoc dl = MI.getDebugLoc();
|
||||
int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
|
||||
|
||||
unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW);
|
||||
unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FP : MSP430::SP);
|
||||
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
|
||||
|
||||
// Skip the saved PC
|
||||
@ -122,7 +122,7 @@ MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
if (!TFI->hasFP(MF))
|
||||
Offset += MF.getFrameInfo()->getStackSize();
|
||||
else
|
||||
Offset += 2; // Skip the saved FPW
|
||||
Offset += 2; // Skip the saved FP
|
||||
|
||||
// Fold imm into offset
|
||||
Offset += MI.getOperand(FIOperandNum + 1).getImm();
|
||||
@ -158,5 +158,5 @@ MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
unsigned MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
|
||||
const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
|
||||
|
||||
return TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW;
|
||||
return TFI->hasFP(MF) ? MSP430::FP : MSP430::SP;
|
||||
}
|
||||
|
||||
@ -46,22 +46,22 @@ def R15B : MSP430Reg<15, "r15">;
|
||||
def subreg_8bit : SubRegIndex<8> { let Namespace = "MSP430"; }
|
||||
|
||||
let SubRegIndices = [subreg_8bit] in {
|
||||
def PCW : MSP430RegWithSubregs<0, "r0", [PCB]>;
|
||||
def SPW : MSP430RegWithSubregs<1, "r1", [SPB]>;
|
||||
def SRW : MSP430RegWithSubregs<2, "r2", [SRB]>;
|
||||
def CGW : MSP430RegWithSubregs<3, "r3", [CGB]>;
|
||||
def FPW : MSP430RegWithSubregs<4, "r4", [FPB]>;
|
||||
def R5W : MSP430RegWithSubregs<5, "r5", [R5B]>;
|
||||
def R6W : MSP430RegWithSubregs<6, "r6", [R6B]>;
|
||||
def R7W : MSP430RegWithSubregs<7, "r7", [R7B]>;
|
||||
def R8W : MSP430RegWithSubregs<8, "r8", [R8B]>;
|
||||
def R9W : MSP430RegWithSubregs<9, "r9", [R9B]>;
|
||||
def R10W : MSP430RegWithSubregs<10, "r10", [R10B]>;
|
||||
def R11W : MSP430RegWithSubregs<11, "r11", [R11B]>;
|
||||
def R12W : MSP430RegWithSubregs<12, "r12", [R12B]>;
|
||||
def R13W : MSP430RegWithSubregs<13, "r13", [R13B]>;
|
||||
def R14W : MSP430RegWithSubregs<14, "r14", [R14B]>;
|
||||
def R15W : MSP430RegWithSubregs<15, "r15", [R15B]>;
|
||||
def PC : MSP430RegWithSubregs<0, "r0", [PCB]>;
|
||||
def SP : MSP430RegWithSubregs<1, "r1", [SPB]>;
|
||||
def SR : MSP430RegWithSubregs<2, "r2", [SRB]>;
|
||||
def CG : MSP430RegWithSubregs<3, "r3", [CGB]>;
|
||||
def FP : MSP430RegWithSubregs<4, "r4", [FPB]>;
|
||||
def R5 : MSP430RegWithSubregs<5, "r5", [R5B]>;
|
||||
def R6 : MSP430RegWithSubregs<6, "r6", [R6B]>;
|
||||
def R7 : MSP430RegWithSubregs<7, "r7", [R7B]>;
|
||||
def R8 : MSP430RegWithSubregs<8, "r8", [R8B]>;
|
||||
def R9 : MSP430RegWithSubregs<9, "r9", [R9B]>;
|
||||
def R10 : MSP430RegWithSubregs<10, "r10", [R10B]>;
|
||||
def R11 : MSP430RegWithSubregs<11, "r11", [R11B]>;
|
||||
def R12 : MSP430RegWithSubregs<12, "r12", [R12B]>;
|
||||
def R13 : MSP430RegWithSubregs<13, "r13", [R13B]>;
|
||||
def R14 : MSP430RegWithSubregs<14, "r14", [R14B]>;
|
||||
def R15 : MSP430RegWithSubregs<15, "r15", [R15B]>;
|
||||
}
|
||||
|
||||
def GR8 : RegisterClass<"MSP430", [i8], 8,
|
||||
@ -74,8 +74,8 @@ def GR8 : RegisterClass<"MSP430", [i8], 8,
|
||||
|
||||
def GR16 : RegisterClass<"MSP430", [i16], 16,
|
||||
// Volatile registers
|
||||
(add R12W, R13W, R14W, R15W, R11W, R10W, R9W, R8W, R7W, R6W, R5W,
|
||||
(add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
|
||||
// Frame pointer, sometimes allocable
|
||||
FPW,
|
||||
FP,
|
||||
// Volatile, but not allocable
|
||||
PCW, SPW, SRW, CGW)>;
|
||||
PC, SP, SR, CG)>;
|
||||
|
||||
13
test/CodeGen/MSP430/asm-clobbers.ll
Normal file
13
test/CodeGen/MSP430/asm-clobbers.ll
Normal file
@ -0,0 +1,13 @@
|
||||
; RUN: llc < %s | FileCheck %s
|
||||
|
||||
target datalayout = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"
|
||||
target triple = "msp430---elf"
|
||||
|
||||
define void @test() {
|
||||
entry:
|
||||
; CHECK-LABEL: test:
|
||||
; CHECK: push.w r10
|
||||
call void asm sideeffect "", "~{r10}"()
|
||||
; CHECK: pop.w r10
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user