6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-08-15 06:29:05 +00:00
Code Issues Projects Releases Wiki Activity

R600: Do not fold single instruction with more that 3 kcache read

Browse Source 
It fixes around 100 tfb piglit tests and 16 glean tests.

NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175183 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vincent Lejeune
2013-02-14 16:57:19 +00:00
parent f846add9ad
commit 7867885737
3 changed files with 55 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/R600/AMDILISelDAGToDAG.cpp
View File

@@ -334,6 +334,8 @@ bool AMDGPUDAGToDAGISel::FoldOperands(unsigned Opcode,
SDValue Operand = Ops[OperandIdx[i] - 1]; SDValue Operand = Ops[OperandIdx[i] - 1];
switch (Operand.getOpcode()) { switch (Operand.getOpcode()) {
case AMDGPUISD::CONST_ADDRESS: { case AMDGPUISD::CONST_ADDRESS: {
if (i == 2)
break;
SDValue CstOffset; SDValue CstOffset;
if (!Operand.getValueType().isVector() && if (!Operand.getValueType().isVector() &&
SelectGlobalValueConstantOffset(Operand.getOperand(0), CstOffset)) { SelectGlobalValueConstantOffset(Operand.getOperand(0), CstOffset)) {

2
lib/Target/R600/R600LowerConstCopy.cpp
View File

@@ -180,7 +180,7 @@ bool R600LowerConstCopy::runOnMachineFunction(MachineFunction &MF) {
int ConstMovSel = int ConstMovSel =
TII->getOperandIdx(CstMov->getOpcode(), R600Operands::SRC0_SEL); TII->getOperandIdx(CstMov->getOpcode(), R600Operands::SRC0_SEL);
unsigned ConstIndex = CstMov->getOperand(ConstMovSel).getImm(); unsigned ConstIndex = CstMov->getOperand(ConstMovSel).getImm();
if (canFoldInBundle(CP, ConstIndex)) { if (MI->isInsideBundle() && canFoldInBundle(CP, ConstIndex)) {
TII->setImmOperand(MI, OpTable[SrcOp][1], ConstIndex); TII->setImmOperand(MI, OpTable[SrcOp][1], ConstIndex);
MI->getOperand(SrcIdx).setReg(AMDGPU::ALU_CONST); MI->getOperand(SrcIdx).setReg(AMDGPU::ALU_CONST);
} else { } else {

52
test/CodeGen/R600/kcache-fold.ll Normal file
View File

@@ -0,0 +1,52 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
; CHECK: MOV T{{[0-9]+\.[XYZW], CBuf0\[[0-9]+\]\.[XYZW]}}
define void @main() {
main_body:
%0 = load <4 x float> addrspace(9)* null
%1 = extractelement <4 x float> %0, i32 0
%2 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 1)
%3 = extractelement <4 x float> %2, i32 0
%4 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 2)
%5 = extractelement <4 x float> %4, i32 0
%6 = fcmp ult float %1, 0.000000e+00
%7 = select i1 %6, float %3, float %5
%8 = load <4 x float> addrspace(9)* null
%9 = extractelement <4 x float> %8, i32 1
%10 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 1)
%11 = extractelement <4 x float> %10, i32 1
%12 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 2)
%13 = extractelement <4 x float> %12, i32 1
%14 = fcmp ult float %9, 0.000000e+00
%15 = select i1 %14, float %11, float %13
%16 = load <4 x float> addrspace(9)* null
%17 = extractelement <4 x float> %16, i32 2
%18 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 1)
%19 = extractelement <4 x float> %18, i32 2
%20 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 2)
%21 = extractelement <4 x float> %20, i32 2
%22 = fcmp ult float %17, 0.000000e+00
%23 = select i1 %22, float %19, float %21
%24 = load <4 x float> addrspace(9)* null
%25 = extractelement <4 x float> %24, i32 3
%26 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 1)
%27 = extractelement <4 x float> %26, i32 3
%28 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 2)
%29 = extractelement <4 x float> %28, i32 3
%30 = fcmp ult float %25, 0.000000e+00
%31 = select i1 %30, float %27, float %29
%32 = call float @llvm.AMDIL.clamp.(float %7, float 0.000000e+00, float 1.000000e+00)
%33 = call float @llvm.AMDIL.clamp.(float %15, float 0.000000e+00, float 1.000000e+00)
%34 = call float @llvm.AMDIL.clamp.(float %23, float 0.000000e+00, float 1.000000e+00)
%35 = call float @llvm.AMDIL.clamp.(float %31, float 0.000000e+00, float 1.000000e+00)
%36 = insertelement <4 x float> undef, float %32, i32 0
%37 = insertelement <4 x float> %36, float %33, i32 1
%38 = insertelement <4 x float> %37, float %34, i32 2
%39 = insertelement <4 x float> %38, float %35, i32 3
call void @llvm.R600.store.swizzle(<4 x float> %39, i32 0, i32 0)
ret void
}
declare float @llvm.AMDIL.clamp.(float, float, float) readnone
declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)