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If val# def is ~0U, meaning it's defined by a PHI, and it's previously split, spill before the barrier because it's impossible to determine if all the defs are spilled in the same spill slot.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58129 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2008-10-25 00:52:41 +00:00
parent f14df02340
commit 78dfef771b
2 changed files with 35 additions and 9 deletions
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20
lib/CodeGen/PreAllocSplitting.cpp
View File

@ -527,21 +527,23 @@ bool PreAllocSplitting::SplitRegLiveInterval(LiveInterval *LI) {
int SS;
unsigned SpillIndex = 0;
MachineInstr *SpillMI = NULL;
if (isAlreadySplit(CurrLI->reg, ValNo->id, SS)) {
// If it's already split, just restore the value. There is no need to spill
// the def again.
} else if (ValNo->def == ~0U) {
bool PrevSpilled = isAlreadySplit(CurrLI->reg, ValNo->id, SS);
if (ValNo->def == ~0U) {
// If it's defined by a phi, we must split just before the barrier.
MachineBasicBlock::iterator SpillPt =
findSpillPoint(BarrierMBB, Barrier, RefsInMBB, SpillIndex);
if (SpillPt == BarrierMBB->begin())
return false; // No gap to insert spill.
// Add spill.
SS = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
if (!PrevSpilled)
// If previously split, reuse the spill slot.
SS = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
TII->storeRegToStackSlot(*BarrierMBB, SpillPt, CurrLI->reg, true, SS, RC);
SpillMI = prior(SpillPt);
LIs->InsertMachineInstrInMaps(SpillMI, SpillIndex);
} else {
} else if (!PrevSpilled) {
// If it's already split, just restore the value. There is no need to spill
// the def again.
// Check if it's possible to insert a spill after the def MI.
MachineBasicBlock::iterator SpillPt =
findNextEmptySlot(DefMBB, DefMI, SpillIndex);
@ -549,8 +551,8 @@ bool PreAllocSplitting::SplitRegLiveInterval(LiveInterval *LI) {
return false; // No gap to insert spill.
SS = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
// Add spill. The store instruction kills the register if def is before the
// barrier in the barrier block.
// Add spill. The store instruction kills the register if def is before
// the barrier in the barrier block.
TII->storeRegToStackSlot(*DefMBB, SpillPt, CurrLI->reg,
DefMBB == BarrierMBB, SS, RC);
SpillMI = prior(SpillPt);
@ -567,7 +569,7 @@ bool PreAllocSplitting::SplitRegLiveInterval(LiveInterval *LI) {
// If live interval is spilled in the same block as the barrier, just
// create a hole in the interval.
if (!DefMBB ||
(SpillIndex && SpillMI->getParent() == BarrierMBB)) {
(SpillMI && SpillMI->getParent() == BarrierMBB)) {
UpdateIntervalForSplit(ValNo, LIs->getUseIndex(SpillIndex)+1,
LIs->getDefIndex(RestoreIndex));

24
test/CodeGen/X86/pre-split4.ll Normal file
View File

@ -0,0 +1,24 @@
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
; RUN: grep {pre-alloc-split} | grep {Number of intervals split} | grep 4
define i32 @main(i32 %argc, i8** %argv) nounwind {
entry:
br label %bb
bb: ; preds = %bb, %entry
%k.0.reg2mem.0 = phi double [ 1.000000e+00, %entry ], [ %6, %bb ] ; <double> [#uses=2]
%Flint.0.reg2mem.0 = phi double [ 0.000000e+00, %entry ], [ %5, %bb ] ; <double> [#uses=1]
%twoThrd.0.reg2mem.0 = phi double [ 0.000000e+00, %entry ], [ %1, %bb ] ; <double> [#uses=1]
%0 = tail call double @llvm.pow.f64(double 0x3FE5555555555555, double 0.000000e+00) ; <double> [#uses=1]
%1 = add double %0, %twoThrd.0.reg2mem.0 ; <double> [#uses=1]
%2 = tail call double @sin(double %k.0.reg2mem.0) nounwind readonly ; <double> [#uses=1]
%3 = mul double 0.000000e+00, %2 ; <double> [#uses=1]
%4 = fdiv double 1.000000e+00, %3 ; <double> [#uses=1]
%5 = add double %4, %Flint.0.reg2mem.0 ; <double> [#uses=1]
%6 = add double %k.0.reg2mem.0, 1.000000e+00 ; <double> [#uses=1]
br label %bb
}
declare double @llvm.pow.f64(double, double) nounwind readonly
declare double @sin(double) nounwind readonly