mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-04-12 07:37:34 +00:00
Revert LoopStrengthReduce.cpp to pre-r94061 for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94123 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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@ -27,7 +27,10 @@ namespace llvm {
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/// and destroy it when finished to allow the release of the associated
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/// memory.
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class SCEVExpander : public SCEVVisitor<SCEVExpander, Value*> {
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public:
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ScalarEvolution &SE;
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private:
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std::map<std::pair<const SCEV *, Instruction *>, AssertingVH<Value> >
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InsertedExpressions;
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std::set<Value*> InsertedValues;
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File diff suppressed because it is too large
Load Diff
@ -1,32 +1,7 @@
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; RUN: llc < %s -march=arm | FileCheck %s
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; This loop is rewritten with an indvar which counts down, which
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; frees up a register from holding the trip count.
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define void @test(i32* %P, i32 %A, i32 %i) nounwind {
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entry:
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; CHECK: str r1, [{{r.*}}, +{{r.*}}, lsl #2]
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icmp eq i32 %i, 0 ; <i1>:0 [#uses=1]
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br i1 %0, label %return, label %bb
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bb: ; preds = %bb, %entry
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%indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2]
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%i_addr.09.0 = sub i32 %i, %indvar ; <i32> [#uses=1]
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%tmp2 = getelementptr i32* %P, i32 %i_addr.09.0 ; <i32*> [#uses=1]
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store i32 %A, i32* %tmp2
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%indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2]
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icmp eq i32 %indvar.next, %i ; <i1>:1 [#uses=1]
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br i1 %1, label %return, label %bb
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return: ; preds = %bb, %entry
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ret void
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}
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; This loop has a non-address use of the count-up indvar, so
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; it'll remain. Now the original store uses a negative-stride address.
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define void @test_with_forced_iv(i32* %P, i32 %A, i32 %i) nounwind {
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entry:
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; CHECK: str r1, [{{r.*}}, -{{r.*}}, lsl #2]
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icmp eq i32 %i, 0 ; <i1>:0 [#uses=1]
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br i1 %0, label %return, label %bb
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@ -36,7 +11,6 @@ bb: ; preds = %bb, %entry
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%i_addr.09.0 = sub i32 %i, %indvar ; <i32> [#uses=1]
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%tmp2 = getelementptr i32* %P, i32 %i_addr.09.0 ; <i32*> [#uses=1]
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store i32 %A, i32* %tmp2
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store i32 %indvar, i32* null
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%indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2]
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icmp eq i32 %indvar.next, %i ; <i1>:1 [#uses=1]
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br i1 %1, label %return, label %bb
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@ -1,5 +1,5 @@
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; RUN: llc < %s -stats |& grep {39.*Number of machine instrs printed}
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; RUN: llc < %s -stats |& not grep {.*Number of re-materialization}
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; RUN: llc < %s -stats |& grep {40.*Number of machine instrs printed}
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; RUN: llc < %s -stats |& grep {.*Number of re-materialization}
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; This test really wants to check that the resultant "cond_true" block only
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; has a single store in it, and that cond_true55 only has code to materialize
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; the constant and do a store. We do *not* want something like this:
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@ -1,4 +1,5 @@
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; RUN: llc < %s -mtriple=arm-apple-darwin -stats -info-output-file - | not grep "Number of re-materialization"
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; RUN: llc < %s -mtriple=arm-apple-darwin
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; RUN: llc < %s -mtriple=arm-apple-darwin -stats -info-output-file - | grep "Number of re-materialization" | grep 3
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%struct.CONTENTBOX = type { i32, i32, i32, i32, i32 }
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%struct.LOCBOX = type { i32, i32, i32, i32 }
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@ -1,29 +1,25 @@
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -relocation-model=pic | FileCheck %s
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; rdar://7387640
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; This now reduces to a single induction variable.
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; TODO: It still gets a GPR shuffle at the end of the loop
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; This is because something in instruction selection has decided
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; that comparing the pre-incremented value with zero is better
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; than comparing the post-incremented value with -4.
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; FIXME: We still need to rewrite array reference iv of stride -4 with loop
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; count iv of stride -1.
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@G = external global i32 ; <i32*> [#uses=2]
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@array = external global i32* ; <i32**> [#uses=1]
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define arm_apcscc void @t() nounwind optsize {
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; CHECK: t:
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; CHECK: mov.w r2, #1000
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; CHECK: mov.w r2, #4000
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; CHECK: movw r3, #1001
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entry:
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%.pre = load i32* @G, align 4 ; <i32> [#uses=1]
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br label %bb
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bb: ; preds = %bb, %entry
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; CHECK: LBB1_1:
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; CHECK: cmp r2, #0
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; CHECK: sub.w r9, r2, #1
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; CHECK: mov r2, r9
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; CHECK: subs r3, #1
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; CHECK: cmp r3, #0
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; CHECK: sub.w r2, r2, #4
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%0 = phi i32 [ %.pre, %entry ], [ %3, %bb ] ; <i32> [#uses=1]
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%indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2]
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%tmp5 = sub i32 1000, %indvar ; <i32> [#uses=1]
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@ -1,6 +1,6 @@
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
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define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
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; CHECK: t1:
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; CHECK: it ne
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; CHECK: cmpne
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@ -20,12 +20,12 @@ cond_next:
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}
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; FIXME: Check for # of unconditional branch after adding branch folding post ifcvt.
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define i32 @t2(i32 %a, i32 %b) nounwind {
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define i32 @t2(i32 %a, i32 %b) {
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entry:
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; CHECK: t2:
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; CHECK: ite gt
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; CHECK: subgt
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; CHECK: ite le
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; CHECK: suble
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; CHECK: subgt
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%tmp1434 = icmp eq i32 %a, %b ; <i1> [#uses=1]
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br i1 %tmp1434, label %bb17, label %bb.outer
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@ -60,14 +60,14 @@ bb17: ; preds = %cond_false, %cond_true, %entry
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@x = external global i32* ; <i32**> [#uses=1]
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define void @foo(i32 %a) nounwind {
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define void @foo(i32 %a) {
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entry:
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%tmp = load i32** @x ; <i32*> [#uses=1]
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store i32 %a, i32* %tmp
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ret void
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}
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define void @t3(i32 %a, i32 %b) nounwind {
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define void @t3(i32 %a, i32 %b) {
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entry:
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; CHECK: t3:
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; CHECK: it lt
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@ -1,5 +1,5 @@
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; RUN: llc < %s -march=x86 -mattr=+sse2 -stats -realign-stack=0 |&\
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; RUN: grep {asm-printer} | grep 34
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; RUN: grep {asm-printer} | grep 31
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target datalayout = "e-p:32:32"
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define void @foo(i32* %mc, i32* %bp, i32* %ms, i32* %xmb, i32* %mpp, i32* %tpmm, i32* %ip, i32* %tpim, i32* %dpp, i32* %tpdm, i32* %bpi, i32 %M) nounwind {
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@ -40,7 +40,7 @@ cond_true: ; preds = %cond_true, %entry
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%tmp137.upgrd.7 = bitcast i32* %tmp137 to <2 x i64>* ; <<2 x i64>*> [#uses=1]
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store <2 x i64> %tmp131, <2 x i64>* %tmp137.upgrd.7
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%tmp147 = add nsw i32 %tmp.10, 8 ; <i32> [#uses=1]
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%tmp.upgrd.8 = icmp ne i32 %tmp147, %M ; <i1> [#uses=1]
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%tmp.upgrd.8 = icmp slt i32 %tmp147, %M ; <i1> [#uses=1]
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%indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1]
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br i1 %tmp.upgrd.8, label %cond_true, label %return
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@ -35,7 +35,7 @@ cond_next36.i: ; preds = %cond_next.i
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bb.i28.i: ; preds = %bb.i28.i, %cond_next36.i
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; CHECK: %bb.i28.i
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; CHECK: addl $2
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; CHECK: addl $-2
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; CHECK: addl $2
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%j.0.reg2mem.0.i16.i = phi i32 [ 0, %cond_next36.i ], [ %indvar.next39.i, %bb.i28.i ] ; <i32> [#uses=2]
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%din_addr.1.reg2mem.0.i17.i = phi double [ 0.000000e+00, %cond_next36.i ], [ %tmp16.i25.i, %bb.i28.i ] ; <double> [#uses=1]
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%tmp1.i18.i = fptosi double %din_addr.1.reg2mem.0.i17.i to i32 ; <i32> [#uses=2]
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@ -1,11 +1,11 @@
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; RUN: llc < %s -march=x86-64 -o %t
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; RUN: not grep inc %t
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; RUN: grep inc %t | count 1
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; RUN: grep dec %t | count 2
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; RUN: grep addq %t | count 10
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; RUN: grep addq %t | count 13
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; RUN: not grep addb %t
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; RUN: grep leaq %t | count 9
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; RUN: grep leal %t | count 2
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; RUN: grep movq %t | count 10
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; RUN: grep leal %t | count 3
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; RUN: grep movq %t | count 5
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; IV users in each of the loops from other loops shouldn't cause LSR
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; to insert new induction variables. Previously it would create a
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@ -1,19 +1,5 @@
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; RUN: llc < %s -march=x86 -relocation-model=static -mtriple=i686-apple-darwin | FileCheck %s -check-prefix=STATIC
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; RUN: llc < %s -march=x86 -relocation-model=pic | FileCheck %s -check-prefix=PIC
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; By starting the IV at -64 instead of 0, a cmp is eliminated,
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; as the flags from the add can be used directly.
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; STATIC: movl $-64, %ecx
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; STATIC: movl %eax, _state+76(%ecx)
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; STATIC: addl $16, %ecx
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; STATIC: jne
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; In PIC mode the symbol can't be folded, so the change-compare-stride
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; trick applies.
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; PIC: cmpl $64
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; RUN: llc < %s -march=x86 | grep cmp | grep 64
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; RUN: llc < %s -march=x86 | not grep inc
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@state = external global [0 x i32] ; <[0 x i32]*> [#uses=4]
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@S = external global [0 x i32] ; <[0 x i32]*> [#uses=4]
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@ -1,10 +1,4 @@
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; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s
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; CHECK: leal 16(%eax), %edx
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; CHECK: align
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; CHECK: addl $4, %edx
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; CHECK: decl %ecx
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; CHECK: jne LBB1_2
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; RUN: llc < %s -mtriple=i386-apple-darwin | grep leal | not grep 16
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%struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32, i32 }
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%struct.bitmap_element = type { %struct.bitmap_element*, %struct.bitmap_element*, i32, [2 x i64] }
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@ -1,159 +0,0 @@
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; RUN: llc < %s -march=x86-64 | FileCheck %s
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target datalayout = "e-p:64:64:64"
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target triple = "x86_64-unknown-unknown"
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; Full strength reduction reduces register pressure from 5 to 4 here.
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; CHECK: full_me:
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; CHECK: movsd (%rsi), %xmm0
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; CHECK: mulsd (%rdx), %xmm0
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; CHECK: movsd %xmm0, (%rdi)
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; CHECK: addq $8, %rsi
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; CHECK: addq $8, %rdx
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; CHECK: addq $8, %rdi
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; CHECK: decq %rcx
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; CHECK: jne
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define void @full_me(double* nocapture %A, double* nocapture %B, double* nocapture %C, i64 %n) nounwind {
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entry:
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%t0 = icmp sgt i64 %n, 0
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br i1 %t0, label %loop, label %return
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loop:
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%i = phi i64 [ %i.next, %loop ], [ 0, %entry ]
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%Ai = getelementptr inbounds double* %A, i64 %i
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%Bi = getelementptr inbounds double* %B, i64 %i
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%Ci = getelementptr inbounds double* %C, i64 %i
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%t1 = load double* %Bi
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%t2 = load double* %Ci
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%m = fmul double %t1, %t2
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store double %m, double* %Ai
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%i.next = add nsw i64 %i, 1
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%exitcond = icmp eq i64 %i.next, %n
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br i1 %exitcond, label %return, label %loop
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return:
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ret void
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}
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; In this test, the counting IV exit value is used, so full strength reduction
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; would not reduce register pressure. IndVarSimplify ought to simplify such
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; cases away, but it's useful here to verify that LSR's register pressure
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; heuristics are working as expected.
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; CHECK: count_me_0:
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; CHECK: movsd (%rsi,%rax,8), %xmm0
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; CHECK: mulsd (%rdx,%rax,8), %xmm0
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; CHECK: movsd %xmm0, (%rdi,%rax,8)
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; CHECK: incq %rax
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; CHECK: cmpq %rax, %rcx
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; CHECK: jne
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define i64 @count_me_0(double* nocapture %A, double* nocapture %B, double* nocapture %C, i64 %n) nounwind {
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entry:
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%t0 = icmp sgt i64 %n, 0
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br i1 %t0, label %loop, label %return
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loop:
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%i = phi i64 [ %i.next, %loop ], [ 0, %entry ]
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%Ai = getelementptr inbounds double* %A, i64 %i
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%Bi = getelementptr inbounds double* %B, i64 %i
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%Ci = getelementptr inbounds double* %C, i64 %i
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%t1 = load double* %Bi
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%t2 = load double* %Ci
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%m = fmul double %t1, %t2
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store double %m, double* %Ai
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%i.next = add nsw i64 %i, 1
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%exitcond = icmp eq i64 %i.next, %n
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br i1 %exitcond, label %return, label %loop
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return:
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%q = phi i64 [ 0, %entry ], [ %i.next, %loop ]
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ret i64 %q
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}
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; In this test, the trip count value is used, so full strength reduction
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; would not reduce register pressure.
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; (though it would reduce register pressure inside the loop...)
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; CHECK: count_me_1:
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; CHECK: movsd (%rsi,%rax,8), %xmm0
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; CHECK: mulsd (%rdx,%rax,8), %xmm0
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; CHECK: movsd %xmm0, (%rdi,%rax,8)
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; CHECK: incq %rax
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; CHECK: cmpq %rax, %rcx
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; CHECK: jne
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define i64 @count_me_1(double* nocapture %A, double* nocapture %B, double* nocapture %C, i64 %n) nounwind {
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entry:
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%t0 = icmp sgt i64 %n, 0
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br i1 %t0, label %loop, label %return
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loop:
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%i = phi i64 [ %i.next, %loop ], [ 0, %entry ]
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%Ai = getelementptr inbounds double* %A, i64 %i
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%Bi = getelementptr inbounds double* %B, i64 %i
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%Ci = getelementptr inbounds double* %C, i64 %i
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%t1 = load double* %Bi
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%t2 = load double* %Ci
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%m = fmul double %t1, %t2
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store double %m, double* %Ai
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%i.next = add nsw i64 %i, 1
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%exitcond = icmp eq i64 %i.next, %n
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br i1 %exitcond, label %return, label %loop
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return:
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%q = phi i64 [ 0, %entry ], [ %n, %loop ]
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ret i64 %q
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}
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; This should be fully strength-reduced to reduce register pressure, however
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; the current heuristics get distracted by all the reuse with the stride-1
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; induction variable first.
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; But even so, be clever and start the stride-1 variable at a non-zero value
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; to eliminate an in-loop immediate value.
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; CHECK: count_me_2:
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; CHECK: movl $5, %eax
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; CHECK: align
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; CHECK: BB4_1:
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; CHECK: movsd (%rdi,%rax,8), %xmm0
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; CHECK: addsd (%rsi,%rax,8), %xmm0
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; CHECK: movsd %xmm0, (%rdx,%rax,8)
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; CHECK: movsd 40(%rdi,%rax,8), %xmm0
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; CHECK: addsd 40(%rsi,%rax,8), %xmm0
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; CHECK: movsd %xmm0, 40(%rdx,%rax,8)
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; CHECK: incq %rax
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; CHECK: cmpq $5005, %rax
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; CHECK: jne
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define void @count_me_2(double* nocapture %A, double* nocapture %B, double* nocapture %C) nounwind {
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entry:
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br label %loop
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loop:
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%i = phi i64 [ 0, %entry ], [ %i.next, %loop ]
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%i5 = add i64 %i, 5
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%Ai = getelementptr double* %A, i64 %i5
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%t2 = load double* %Ai
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%Bi = getelementptr double* %B, i64 %i5
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%t4 = load double* %Bi
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%t5 = fadd double %t2, %t4
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%Ci = getelementptr double* %C, i64 %i5
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store double %t5, double* %Ci
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%i10 = add i64 %i, 10
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%Ai10 = getelementptr double* %A, i64 %i10
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%t9 = load double* %Ai10
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%Bi10 = getelementptr double* %B, i64 %i10
|
||||
%t11 = load double* %Bi10
|
||||
%t12 = fadd double %t9, %t11
|
||||
%Ci10 = getelementptr double* %C, i64 %i10
|
||||
store double %t12, double* %Ci10
|
||||
%i.next = add i64 %i, 1
|
||||
%exitcond = icmp eq i64 %i.next, 5000
|
||||
br i1 %exitcond, label %return, label %loop
|
||||
|
||||
return:
|
||||
ret void
|
||||
}
|
@ -4,9 +4,9 @@
|
||||
; RUN: not grep sar %t
|
||||
; RUN: not grep shl %t
|
||||
; RUN: grep add %t | count 2
|
||||
; RUN: grep inc %t | count 3
|
||||
; RUN: grep inc %t | count 4
|
||||
; RUN: grep dec %t | count 2
|
||||
; RUN: grep lea %t | count 3
|
||||
; RUN: grep lea %t | count 2
|
||||
|
||||
; Optimize away zext-inreg and sext-inreg on the loop induction
|
||||
; variable using trip-count information.
|
||||
@ -127,9 +127,6 @@ return:
|
||||
ret void
|
||||
}
|
||||
|
||||
; TODO: If we could handle all the loads and stores as post-inc users, we could
|
||||
; use {-1,+,1} in the induction variable register, and we'd get another inc,
|
||||
; one fewer add, and a comparison with zero.
|
||||
define void @another_count_up(double* %d, i64 %n) nounwind {
|
||||
entry:
|
||||
br label %loop
|
||||
|
@ -1,4 +1,5 @@
|
||||
; RUN: llc -march=x86-64 < %s -o - | grep {cmpl \\$\[1\], %}
|
||||
; RUN: opt < %s -loop-reduce -S | grep ugt
|
||||
; PR2535
|
||||
|
||||
@.str = internal constant [4 x i8] c"%d\0A\00"
|
||||
|
||||
@ -15,7 +16,7 @@ forbody:
|
||||
%add166 = or i32 %mul15, 1 ; <i32> [#uses=1] *
|
||||
call i32 (i8*, ...)* @printf( i8* noalias getelementptr ([4 x i8]* @.str, i32 0, i32 0), i32 %add166 ) nounwind
|
||||
%inc = add i32 %i.0, 1 ; <i32> [#uses=3]
|
||||
%cmp = icmp ne i32 %inc, 1027 ; <i1> [#uses=1]
|
||||
%cmp = icmp ult i32 %inc, 1027 ; <i1> [#uses=1]
|
||||
br i1 %cmp, label %forbody, label %afterfor
|
||||
|
||||
afterfor: ; preds = %forcond
|
||||
|
@ -1,9 +1,10 @@
|
||||
; RUN: llc < %s -o - | grep {testl %ecx, %ecx}
|
||||
; RUN: llc %s -o - --x86-asm-syntax=att | grep {cmpl \$4}
|
||||
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
|
||||
target triple = "x86_64-apple-darwin9"
|
||||
|
||||
; The comparison happens before the relevant use, but it can still be rewritten
|
||||
; to compare with zero.
|
||||
; This is like change-compare-stride-trickiness-1.ll except the comparison
|
||||
; happens before the relevant use, so the comparison stride can't be
|
||||
; easily changed.
|
||||
|
||||
define void @foo() nounwind {
|
||||
entry:
|
||||
|
@ -19,7 +19,7 @@ bb3: ; preds = %bb1
|
||||
%tmp4 = add i32 %c_addr.1, -1 ; <i32> [#uses=1]
|
||||
%c_addr.1.be = select i1 %tmp2, i32 %tmp3, i32 %tmp4 ; <i32> [#uses=1]
|
||||
%indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1]
|
||||
; CHECK: add i32 %lsr.iv, -1
|
||||
; CHECK: sub i32 %lsr.iv, 1
|
||||
br label %bb6
|
||||
|
||||
bb6: ; preds = %bb3, %entry
|
||||
|
Loading…
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Reference in New Issue
Block a user