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Add AVX SSE3 replicate and convert instructions

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107375 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2010-07-01 02:33:39 +00:00
parent 5c87bf64d6
commit 79b634c244
3 changed files with 117 additions and 22 deletions
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67
lib/Target/X86/X86InstrSSE.td
View File

@ -3161,10 +3161,18 @@ let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
[(set VR128:$dst, (v4i32 immAllOnesV))]>;
//===---------------------------------------------------------------------===//
// SSE3 Instructions
// SSE3 - Conversion Instructions
//===---------------------------------------------------------------------===//
// Conversion Instructions
let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in {
def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
"vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
"vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
"vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
}
def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
"cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
@ -3174,33 +3182,44 @@ def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
"cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
// Move Instructions
def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
"movshdup\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (v4f32 (movshdup
VR128:$src, (undef))))]>;
def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
"movshdup\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (movshdup
(memopv4f32 addr:$src), (undef)))]>;
//===---------------------------------------------------------------------===//
// SSE3 - Move Instructions
//===---------------------------------------------------------------------===//
def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
"movsldup\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (v4f32 (movsldup
// Replicate Single FP
multiclass sse3_replicate_sfp<bits<8> op, PatFrag rep_frag, string OpcodeStr> {
def rr : S3SI<op, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
[(set VR128:$dst, (v4f32 (rep_frag
VR128:$src, (undef))))]>;
def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
"movsldup\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (movsldup
def rm : S3SI<op, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
[(set VR128:$dst, (rep_frag
(memopv4f32 addr:$src), (undef)))]>;
}
def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
"movddup\t{$src, $dst|$dst, $src}",
[(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
"movddup\t{$src, $dst|$dst, $src}",
let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in {
defm VMOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "vmovshdup">, VEX;
defm VMOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "vmovsldup">, VEX;
}
defm MOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "movshdup">;
defm MOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "movsldup">;
// Replicate Double FP
multiclass sse3_replicate_dfp<string OpcodeStr> {
def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
[(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
[(set VR128:$dst,
(v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
(undef))))]>;
}
let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in
defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
defm MOVDDUP : sse3_replicate_dfp<"movddup">;
def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
(undef)),
@ -3217,6 +3236,10 @@ def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
(MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
}
//===---------------------------------------------------------------------===//
// SSE3 Instructions
//===---------------------------------------------------------------------===//
// Arithmetic
let Constraints = "$src1 = $dst" in {
def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,

36
test/MC/AsmParser/X86/x86_32-encoding.s
View File

@ -11530,3 +11530,39 @@
// CHECK: encoding: [0xc5,0xfa,0x7e,0x08]
vmovq (%eax), %xmm1
// CHECK: vcvtpd2dq %xmm1, %xmm2
// CHECK: encoding: [0xc5,0xfb,0xe6,0xd1]
vcvtpd2dq %xmm1, %xmm2
// CHECK: vcvtdq2pd %xmm1, %xmm2
// CHECK: encoding: [0xc5,0xfa,0xe6,0xd1]
vcvtdq2pd %xmm1, %xmm2
// CHECK: vcvtdq2pd (%eax), %xmm2
// CHECK: encoding: [0xc5,0xfa,0xe6,0x10]
vcvtdq2pd (%eax), %xmm2
// CHECK: vmovshdup %xmm1, %xmm2
// CHECK: encoding: [0xc5,0xfa,0x16,0xd1]
vmovshdup %xmm1, %xmm2
// CHECK: vmovshdup (%eax), %xmm2
// CHECK: encoding: [0xc5,0xfa,0x16,0x10]
vmovshdup (%eax), %xmm2
// CHECK: vmovsldup %xmm1, %xmm2
// CHECK: encoding: [0xc5,0xfa,0x12,0xd1]
vmovsldup %xmm1, %xmm2
// CHECK: vmovsldup (%eax), %xmm2
// CHECK: encoding: [0xc5,0xfa,0x12,0x10]
vmovsldup (%eax), %xmm2
// CHECK: vmovddup %xmm1, %xmm2
// CHECK: encoding: [0xc5,0xfb,0x12,0xd1]
vmovddup %xmm1, %xmm2
// CHECK: vmovddup (%eax), %xmm2
// CHECK: encoding: [0xc5,0xfb,0x12,0x10]
vmovddup (%eax), %xmm2

36
test/MC/AsmParser/X86/x86_64-encoding.s
View File

@ -1578,3 +1578,39 @@ pshufb CPI1_0(%rip), %xmm1
// CHECK: encoding: [0xc4,0x61,0xf9,0x7e,0xf0]
vmovq %xmm14, %rax
// CHECK: vcvtpd2dq %xmm11, %xmm12
// CHECK: encoding: [0xc4,0x41,0x7b,0xe6,0xe3]
vcvtpd2dq %xmm11, %xmm12
// CHECK: vcvtdq2pd %xmm11, %xmm12
// CHECK: encoding: [0xc4,0x41,0x7a,0xe6,0xe3]
vcvtdq2pd %xmm11, %xmm12
// CHECK: vcvtdq2pd (%rax), %xmm12
// CHECK: encoding: [0xc5,0x7a,0xe6,0x20]
vcvtdq2pd (%rax), %xmm12
// CHECK: vmovshdup %xmm11, %xmm12
// CHECK: encoding: [0xc4,0x41,0x7a,0x16,0xe3]
vmovshdup %xmm11, %xmm12
// CHECK: vmovshdup (%rax), %xmm12
// CHECK: encoding: [0xc5,0x7a,0x16,0x20]
vmovshdup (%rax), %xmm12
// CHECK: vmovsldup %xmm11, %xmm12
// CHECK: encoding: [0xc4,0x41,0x7a,0x12,0xe3]
vmovsldup %xmm11, %xmm12
// CHECK: vmovsldup (%rax), %xmm12
// CHECK: encoding: [0xc5,0x7a,0x12,0x20]
vmovsldup (%rax), %xmm12
// CHECK: vmovddup %xmm11, %xmm12
// CHECK: encoding: [0xc4,0x41,0x7b,0x12,0xe3]
vmovddup %xmm11, %xmm12
// CHECK: vmovddup (%rax), %xmm12
// CHECK: encoding: [0xc5,0x7b,0x12,0x20]
vmovddup (%rax), %xmm12