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Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by element size. Instead,

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all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with
the immediate shifted left to reflect the increased element size.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118183 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2010-11-03 18:16:27 +00:00
parent d5ce456161
commit 7a25825033
2 changed files with 32 additions and 10 deletions
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38
lib/Target/ARM/ARMInstrNEON.td
View File

@ -4241,15 +4241,37 @@ class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
let Inst{11-8} = index{3-0}; let Inst{11-8} = index{3-0};
} }
def VEXTd8 : VEXTd<"vext", "8", v8i8>; def VEXTd8 : VEXTd<"vext", "8", v8i8> {
def VEXTd16 : VEXTd<"vext", "16", v4i16>; let Inst{11-8} = index{3-0};
def VEXTd32 : VEXTd<"vext", "32", v2i32>; }
def VEXTdf : VEXTd<"vext", "32", v2f32>; def VEXTd16 : VEXTd<"vext", "16", v4i16> {
let Inst{11-9} = index{2-0};
let Inst{8} = 0b0;
}
def VEXTd32 : VEXTd<"vext", "32", v2i32> {
let Inst{11-10} = index{1-0};
let Inst{9-8} = 0b00;
}
def VEXTdf : VEXTd<"vext", "32", v2f32> {
let Inst{11} = index{0};
let Inst{10-8} = 0b000;
}
def VEXTq8 : VEXTq<"vext", "8", v16i8>; def VEXTq8 : VEXTq<"vext", "8", v16i8> {
def VEXTq16 : VEXTq<"vext", "16", v8i16>; let Inst{11-8} = index{3-0};
def VEXTq32 : VEXTq<"vext", "32", v4i32>; }
def VEXTqf : VEXTq<"vext", "32", v4f32>; def VEXTq16 : VEXTq<"vext", "16", v8i16> {
let Inst{11-9} = index{2-0};
let Inst{8} = 0b0;
}
def VEXTq32 : VEXTq<"vext", "32", v4i32> {
let Inst{11-10} = index{1-0};
let Inst{9-8} = 0b00;
}
def VEXTqf : VEXTq<"vext", "32", v4f32> {
let Inst{11} = index{0};
let Inst{10-8} = 0b000;
}
// VTRN : Vector Transpose // VTRN : Vector Transpose

4
test/MC/ARM/neon-shuffle-encoding.s
View File

@ -8,9 +8,9 @@
vext.8 q8, q9, q8, #3 vext.8 q8, q9, q8, #3
@ CHECK: vext.8 q8, q9, q8, #7 @ encoding: [0xe0,0x07,0xf2,0xf2] @ CHECK: vext.8 q8, q9, q8, #7 @ encoding: [0xe0,0x07,0xf2,0xf2]
vext.8 q8, q9, q8, #7 vext.8 q8, q9, q8, #7
@ CHECK: vext.16 d16, d17, d16, #3 @ encoding: [0xa0,0x03,0xf1,0xf2] @ CHECK: vext.16 d16, d17, d16, #3 @ encoding: [0xa0,0x06,0xf1,0xf2]
vext.16 d16, d17, d16, #3 vext.16 d16, d17, d16, #3
@ CHECK: vext.32 q8, q9, q8, #3 @ encoding: [0xe0,0x03,0xf2,0xf2] @ CHECK: vext.32 q8, q9, q8, #3 @ encoding: [0xe0,0x0c,0xf2,0xf2]
vext.32 q8, q9, q8, #3 vext.32 q8, q9, q8, #3
@ CHECK: vtrn.8 d17, d16 @ encoding: [0xa0,0x10,0xf2,0xf3] @ CHECK: vtrn.8 d17, d16 @ encoding: [0xa0,0x10,0xf2,0xf3]
vtrn.8 d17, d16 vtrn.8 d17, d16