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Update tests.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138116 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-08-19 22:19:48 +00:00
parent c0f3a1d860
commit 7a32fa1c78
4 changed files with 8 additions and 4 deletions
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4
lib/Target/ARM/ARMInstrThumb.td
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@ -1114,6 +1114,10 @@ def tRSB : // A8.6.141
"rsb", "\t$Rd, $Rn, #0", "rsb", "\t$Rd, $Rn, #0",
[(set tGPR:$Rd, (ineg tGPR:$Rn))]>; [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
def : InstAlias<"neg${s}${p} $Rd, $Rm",
(tRSB tGPR:$Rd, CPSR, tGPR:$Rm, pred:$p)>,
Requires<[IsThumb]>;
// Subtract with carry register // Subtract with carry register
let Uses = [CPSR] in let Uses = [CPSR] in
def tSBC : // A8.6.151 def tSBC : // A8.6.151

4
test/CodeGen/ARM/avoid-cpsr-rmw.ll
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@ -6,9 +6,9 @@
define i32 @t(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone { define i32 @t(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
entry: entry:
; CHECK: t: ; CHECK: t:
; CHECK: muls r2, r3, r2 ; CHECK: muls r2, r2, r3
; CHECK-NEXT: mul r0, r0, r1 ; CHECK-NEXT: mul r0, r0, r1
; CHECK-NEXT: muls r0, r2, r0 ; CHECK-NEXT: muls r0, r0, r2
%0 = mul nsw i32 %a, %b %0 = mul nsw i32 %a, %b
%1 = mul nsw i32 %c, %d %1 = mul nsw i32 %c, %d
%2 = mul nsw i32 %0, %1 %2 = mul nsw i32 %0, %1

2
test/CodeGen/Thumb2/thumb2-mls.ll
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@ -15,5 +15,5 @@ define i32 @f2(i32 %a, i32 %b, i32 %c) {
ret i32 %tmp2 ret i32 %tmp2
} }
; CHECK: f2: ; CHECK: f2:
; CHECK: muls r0, r1 ; CHECK: muls r0, r0, r1

2
test/CodeGen/Thumb2/thumb2-mul.ll
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@ -2,7 +2,7 @@
define i32 @f1(i32 %a, i32 %b, i32 %c) { define i32 @f1(i32 %a, i32 %b, i32 %c) {
; CHECK: f1: ; CHECK: f1:
; CHECK: muls r0, r1 ; CHECK: muls r0, r0, r1
%tmp = mul i32 %a, %b %tmp = mul i32 %a, %b
ret i32 %tmp ret i32 %tmp
} }